From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpout.efficios.com (smtpout.efficios.com [IPv6:2607:5300:203:b2ee::31e5]) by sourceware.org (Postfix) with ESMTPS id 97879385DC27 for ; Thu, 1 Feb 2024 19:37:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 97879385DC27 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=efficios.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=efficios.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 97879385DC27 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:5300:203:b2ee::31e5 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706816249; cv=none; b=vfALmIWnFPIQxzNGLIySy7T2PYoi2a0txn2A5VV6wTeFFrL2xlitY9vM3wUC4Osl5qrdc/i0Z273aUUXVc+t1U9rr6BNk3GL0qP1yuTlD/nWwIe0wUWA0XBbnnJM2SgaBLzZ8fMmYTMrTQtoM8OpBxpfm9Xii4gjejFfg/WAqfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706816249; c=relaxed/simple; bh=gYj4TIK8gVbjfXVMldsYjD2iyu5Fir25xU9uUsqQQFQ=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=jQVm4op4SMJ9GpmrH4SSKdwQ/IRokHVdcnVkaJ+bmZCUZOz9pd196zYqBGzFdM1HKzafTCnoPI05VK6qKeVzS8w/u7qTrlUKTeliNcH5LLQxlT0avb6z01dx3TpCV5OU4nZYeLUrLYZU9Tb1UpLnEh58whIrX7vFjzxRq2u4NvA= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=efficios.com; s=smtpout1; t=1706816246; bh=gYj4TIK8gVbjfXVMldsYjD2iyu5Fir25xU9uUsqQQFQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m/50fgV7P3R0fPkwwYDe76BgO097svfWD5IqK3jsY/jteQ4ZyV1gW0Po009vKLN99 eWcWdGGm7d3nhx+9F0BMpkTuf8Co7XlB8Um9P7x0PFlob3i/dHJwkEWGxZw9y1NIMZ FOhtNOykPjaaXOBrXPQxyojHRdCmFEtYqmgdQDU+qchX/PBbyWsvttLOOdfcgcTo0C kuoACCJX7xNKARe3lyaCIqu7lWsMZWfondFa1O/ZfOzI2cYzy1xCz/+DSC0/2wnJL9 Ibbq0WUDN384InjJCZ7THHVXdg4f0tL2lGTwoQunjljp5oRNUoEoyiBphqLTkAQ/WN XGnyysMRS5JIQ== Received: from laptop-mjeanson.internal.efficios.com (192-222-143-198.qc.cable.ebox.net [192.222.143.198]) by smtpout.efficios.com (Postfix) with ESMTPSA id 4TQq1L1cg7zX41; Thu, 1 Feb 2024 14:37:26 -0500 (EST) From: Michael Jeanson To: libc-alpha@sourceware.org Cc: Michael Jeanson , Florian Weimer , Carlos O'Donell , Mathieu Desnoyers Subject: [PATCH v7 7/8] aarch64: Add rseq_load32_load32_relaxed Date: Thu, 1 Feb 2024 14:36:47 -0500 Message-Id: <20240201193648.584917-8-mjeanson@efficios.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240201193648.584917-1-mjeanson@efficios.com> References: <20240201193648.584917-1-mjeanson@efficios.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Mathieu Desnoyers Implement rseq_load32_load32_relaxed() for the aarch64 architecture. This static inline function implements a rseq critical section to load two 32-bit integer values atomically with respect to preemption and signal delivery. This implementation is imported from the librseq project. Signed-off-by: Mathieu Desnoyers Signed-off-by: Michael Jeanson --- .../unix/sysv/linux/aarch64/rseq-internal.h | 173 ++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 sysdeps/unix/sysv/linux/aarch64/rseq-internal.h diff --git a/sysdeps/unix/sysv/linux/aarch64/rseq-internal.h b/sysdeps/unix/sysv/linux/aarch64/rseq-internal.h new file mode 100644 index 0000000000..3c03f67dbe --- /dev/null +++ b/sysdeps/unix/sysv/linux/aarch64/rseq-internal.h @@ -0,0 +1,173 @@ +/* Restartable Sequences internal API. aarch64 macros. + Copyright (C) 2023 Free Software Foundation, Inc. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +#define RSEQ_ASM_TMP_REG32 "w15" +#define RSEQ_ASM_TMP_REG "x15" +#define RSEQ_ASM_TMP_REG_2 "x14" + +#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \ + post_commit_offset, abort_ip) \ + " .pushsection __rseq_cs, \"aw\"\n" \ + " .balign 32\n" \ + __rseq_str(label) ":\n" \ + " .long " __rseq_str(version) ", " __rseq_str(flags) "\n" \ + " .quad " __rseq_str(start_ip) ", " \ + __rseq_str(post_commit_offset) ", " \ + __rseq_str(abort_ip) "\n" \ + " .popsection\n\t" \ + " .pushsection __rseq_cs_ptr_array, \"aw\"\n" \ + " .quad " __rseq_str(label) "b\n" \ + " .popsection\n" + +#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \ + __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \ + (post_commit_ip - start_ip), abort_ip) + +/* + * Exit points of a rseq critical section consist of all instructions outside + * of the critical section where a critical section can either branch to or + * reach through the normal course of its execution. The abort IP and the + * post-commit IP are already part of the __rseq_cs section and should not be + * explicitly defined as additional exit points. Knowing all exit points is + * useful to assist debuggers stepping over the critical section. + */ +#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \ + " .pushsection __rseq_exit_point_array, \"aw\"\n" \ + " .quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n" \ + " .popsection\n" + +#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \ + " adrp " RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n" \ + " add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ + ", :lo12:" __rseq_str(cs_label) "\n" \ + " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n" \ + __rseq_str(label) ":\n" + +#define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \ + " b 222f\n" \ + " .inst " __rseq_str(RSEQ_SIG_CODE) "\n" \ + __rseq_str(label) ":\n" \ + " b %l[" __rseq_str(abort_label) "]\n" \ + "222:\n" + +#define RSEQ_ASM_OP_STORE(value, var) \ + " str %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_STORE_RELEASE(value, var) \ + " stlr %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \ + RSEQ_ASM_OP_STORE(value, var) \ + __rseq_str(post_commit_label) ":\n" + +#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \ + RSEQ_ASM_OP_STORE_RELEASE(value, var) \ + __rseq_str(post_commit_label) ":\n" + +#define RSEQ_ASM_OP_CMPEQ(var, expect, label) \ + " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \ + " sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ + ", %[" __rseq_str(expect) "]\n" \ + " cbnz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n" + +#define RSEQ_ASM_OP_CMPEQ32(var, expect, label) \ + " ldr " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" \ + " sub " RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32 \ + ", %w[" __rseq_str(expect) "]\n" \ + " cbnz " RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n" + +#define RSEQ_ASM_OP_CMPNE(var, expect, label) \ + " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \ + " sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ + ", %[" __rseq_str(expect) "]\n" \ + " cbz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n" + +#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \ + RSEQ_ASM_OP_CMPEQ32(current_cpu_id, cpu_id, label) + +#define RSEQ_ASM_OP_R_LOAD(var) \ + " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_R_STORE(var) \ + " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_R_LOAD32(var) \ + " ldr " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_R_STORE32(var) \ + " str " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" + +#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \ + " ldr " RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG \ + ", %[" __rseq_str(offset) "]]\n" + +#define RSEQ_ASM_OP_R_ADD(count) \ + " add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ + ", %[" __rseq_str(count) "]\n" + +#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \ + " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \ + __rseq_str(post_commit_label) ":\n" + +#define RSEQ_ASM_OP_R_FINAL_STORE32(var, post_commit_label) \ + " str " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" \ + __rseq_str(post_commit_label) ":\n" + +#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \ + " cbz %[" __rseq_str(len) "], 333f\n" \ + " mov " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n" \ + "222: sub " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n" \ + " ldrb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]" \ + ", " RSEQ_ASM_TMP_REG_2 "]\n" \ + " strb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]" \ + ", " RSEQ_ASM_TMP_REG_2 "]\n" \ + " cbnz " RSEQ_ASM_TMP_REG_2 ", 222b\n" \ + "333:\n" + +/* + * Load @src1 (32-bit) into @dst1 and load @src2 (32-bit) into @dst2. + */ +#define RSEQ_HAS_LOAD32_LOAD32_RELAXED 1 +static __always_inline int +rseq_load32_load32_relaxed(uint32_t *dst1, uint32_t *src1, + uint32_t *dst2, uint32_t *src2) +{ + __asm__ __volatile__ goto ( + RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_OP_R_LOAD32(src1) + RSEQ_ASM_OP_R_STORE32(dst1) + RSEQ_ASM_OP_R_LOAD32(src2) + RSEQ_ASM_OP_R_FINAL_STORE32(dst2, 3) + RSEQ_ASM_DEFINE_ABORT(4, abort) + : /* gcc asm goto does not allow outputs */ + : [rseq_cs] "m" (rseq_get_area()->rseq_cs), + [dst1] "Qo" (*dst1), + [dst2] "Qo" (*dst2), + [src1] "Qo" (*src1), + [src2] "Qo" (*src2) + : "memory", RSEQ_ASM_TMP_REG + : abort + ); + rseq_after_asm_goto(); + return 0; +abort: + rseq_after_asm_goto(); + return -1; +} -- 2.34.1