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[95.217.130.239]) by smtp.gmail.com with ESMTPSA id b14-20020a056512060e00b00516d217f688sm169759lfe.295.2024.04.18.02.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 02:46:39 -0700 (PDT) From: =?UTF-8?q?Christoph=20M=C3=BCllner?= To: libc-alpha@sourceware.org, Adhemerval Zanella , Palmer Dabbelt , Darius Rad , Andrew Waterman , Philipp Tomsich , Evan Green , Kito Cheng , Jeff Law , Vineet Gupta Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH 0/3] RISC-V: Use WRS.STO for atomic_spin_nop Date: Thu, 18 Apr 2024 11:46:32 +0200 Message-ID: <20240418094635.3502009-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This series utilizes the recently introduced hwprobe() and ifunc support in RISC-V to implement atomic_spin_nop. The generic code uses the PAUSE instruction (specified in Zihintpause as HINT instruction). If hwprobe() report availability of Zawrs, then WRS.STO is used instead. All specification are ratified. However, The second patch is not ready to land in glibc yet, because the RISCV_HWPROBE_EXT_ZAWRS macro is not defined in upstream Linux yet (there is just a patch from Andrew Jones on LKML). Therefore, this patch is marked as RFC. See also: https://lore.kernel.org/all/20240315134009.580167-10-ajones@ventanamicro.com/ The first patch of this series imports all HWPROBE macros from Linux 6.8. As this patch has not further dependencies, it could be merged any time. This patch was tested with a simple test code that calls pthread_spin_lock() twice (triggering the spinning). This program was compiled for rv64gc and executed using QEMU. A small modification in QEMU was used to report if WRS.STO was executed (-cpu "rv64,zawrs=false" vs -cpu "rv64,zawrs=true"). Christoph Müllner (3): RISC-V: Sync hwprobe: Sync extension bits with Linux 6.8 RISC-V: hwprobe: Add Zawrs test bit RISC-V: Implement CPU yielding for busy loops with Zihintpause/Zawrs sysdeps/riscv/multiarch/cpu-relax_generic.S | 31 +++++++++++++++ sysdeps/riscv/multiarch/cpu-relax_zawrs.S | 28 +++++++++++++ .../unix/sysv/linux/riscv/atomic-machine.h | 3 ++ .../unix/sysv/linux/riscv/multiarch/Makefile | 8 ++++ .../sysv/linux/riscv/multiarch/cpu-relax.c | 39 +++++++++++++++++++ .../linux/riscv/multiarch/ifunc-impl-list.c | 32 +++++++++++++-- sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h | 30 ++++++++++++++ 7 files changed, 167 insertions(+), 4 deletions(-) create mode 100644 sysdeps/riscv/multiarch/cpu-relax_generic.S create mode 100644 sysdeps/riscv/multiarch/cpu-relax_zawrs.S create mode 100644 sysdeps/unix/sysv/linux/riscv/multiarch/cpu-relax.c -- 2.44.0