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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a24-20020a1709065f9800b00a526fcac8aesm2238663eju.208.2024.04.19.07.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 07:09:17 -0700 (PDT) Date: Fri, 19 Apr 2024 16:09:17 +0200 From: Andrew Jones To: Palmer Dabbelt Cc: Vineet Gupta , Charlie Jenkins , christoph.muellner@vrull.eu, libc-alpha@sourceware.org, adhemerval.zanella@linaro.org, Darius Rad , Andrew Waterman , philipp.tomsich@vrull.eu, Evan Green , kito.cheng@sifive.com, jeffreyalaw@gmail.com Subject: Re: [RFC PATCH 3/3] RISC-V: Implement CPU yielding for busy loops with Zihintpause/Zawrs Message-ID: <20240419-3edb96288d5199abc7081fd7@orel> References: <46e0cfcc-db0f-46fd-8e3f-707fbf656531@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Apr 18, 2024 at 02:10:42PM -0700, Palmer Dabbelt wrote: > On Thu, 18 Apr 2024 13:36:32 PDT (-0700), Vineet Gupta wrote: > > On 4/18/24 13:19, Christoph Müllner wrote: > > > > This has the same forward progress/eventual success violation as the > > > > code you sent for GCC and Linux does. It doesn't really matter if the > > > > user of the reservation is in a builtin, an asm block, or a function. > > > > The compiler just doesn't know about those reservation rules and isn't > > > > going to generate code that follows them. > > > I see. The main issue is that we don't have a valid reservation when > > > calling WRS, > > > so the whole use of Zawrs instructions is pointless. > > > So the only way to move Zawrs forward would be to adjust the locking routines > > > (introducing new primitives that have to be implemented for all architectures). > > > > Not explicitly anyways - the generic fallback will take care of every > > arch, except SPARC/x86 which implement atomic_spin_nop wth pause like > > semantics, but even they don't need to change at all if we implement new > > API atomic_load_and_spin_if_cond_whatever ()  in terms of existing > > atomic_spin_nop () > > Ya, sounds about right. > > IIRC I just hooked some of the LLL macros when doing the POC/estimates, but > it was at least a year ago so I forget exactly how it all fit together. > Whatever it is, they end up with basically the same > load->cond->lr->beq->{wrs,sc} patterns as a bunch of the Linux routines > should have (sort of a test-and-test-and-set type pattern, or how arm64 does > the load-and-cmpxchg routines). > > Adding Charlie and Drew, as we were talking about the Linux side of things > recently. I've just now posted another version [1]. [1] https://lore.kernel.org/all/20240419135321.70781-8-ajones@ventanamicro.com/ Thanks, drew