Re: [PATCH v6 3/3] RISC-V: Implement TLS Descriptors.

[Adhemerval Zanella Netto <adhemerval.zanella@linaro.org>]

On 29/03/24 03:18, Tatsuyuki Ishi wrote:
> This is mostly based off AArch64 implementation, with some adaptations to
> different TLS DTV offsets and calling conventions.
> 
> As we have not officially committed to a vector calling convention, all
> vector registers are saved in the calling convention wrapper. This can be
> revisited once we decide which registers will be callee-saved.
> ---

> +/* The fast path does not call function and does not need to align sp, but
> +   to simplify handling when going into the slow path, keep sp aligned all
> +   the time.
> + */
> +#define FRAME_SIZE_FAST (-((-3 * SZREG) & ALMASK))
> +
> +/* The slow path save slot layout, from lower address to higher address, is:
> +   1. 32 vector registers
> +   2. 12 GP registers
> +   3. 20 FP registers
> +   4. 3 vector CSR registers
> +
> +   1. has machine-dependent size, and hence is not included in FRAME_SIZE_SLOW.
> +   Additionally, the vector register save area needs to be naturally aligned:
> +   this is satisfied as a side effect of 16-byte stack alignment.
> +   The size of vector save area, OTOH, also needs to satisfy stack alignment, as
> +   implementations can have vector registers smaller than 16 bytes.
> +   For now, the size is guaranteed to be a multiple of 16 as we save all 32 vector registers.
> + */
> +#if defined(__riscv_float_abi_soft)
> +# define FRAME_SIZE_SLOW (-((-12 * SZREG) & ALMASK))
> +#elif defined(__riscv_vector)
> +# define FRAME_SIZE_SLOW (-((-15 * SZREG - 20 * SZFREG) & ALMASK))

We already have 6 different RISC-V abis on build-many-glibcs.py, plus
the ZBB/XTHREADB usage on string-fza.h. With this we will another 
sub-variant we will need to build/check, which will make RISC-V even
more MIPS-like with its unfeasible number of ABIs.

Maybe a better option, now that glibc has internally riscv_hwprobe
support and that RVV is only support for 6.5, to use instead of adding
another ABI variant. 

It could either through ifunc variants, like x86, or by embedding the
ABI check within the _dl_tlsdesc_dynamic, like ARM.