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From: Bruno Haible <bruno@clisp.org>
To: libc-alpha@sourceware.org,
	Adhemerval Zanella <adhemerval.zanella@linaro.org>
Subject: Re: [PATCH v2 2/3] i686: Do not raise exception traps on fesetexcept (BZ 30989)
Date: Mon, 30 Oct 2023 16:21:42 +0100	[thread overview]
Message-ID: <5280730.l52yBJDM9G@nimes> (raw)
In-Reply-To: <20231024113716.3911015-3-adhemerval.zanella@linaro.org>

[-- Attachment #1: Type: text/plain, Size: 717 bytes --]

Hi Adhemerval,

In the error case, the new code mistakenly masks all floating-point
exceptions (i.e. as if someone had called fedisableexcept (FE_ALL_EXCEPT)).
This is because the FNSTENV instruction is documented as
   "Saves the current FPU operating environment at the memory
    location specified with the destination operand, and then
    masks all floating-point exceptions."

The mistake came from my initial proposed fix of BZ 30990. Sorry about that.

Here's a proposed fix, on top of your patch. I've verified that the sequence
of instructions
    __asm__ ("fnstenv %0" : "=m" (*&temp));
    __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word));
does restore the exceptions trapping bits.

Bruno


[-- Attachment #2: BZ30989-fnstenv-fix.diff --]
[-- Type: text/x-patch, Size: 1249 bytes --]

diff --git a/sysdeps/i386/fpu/fesetexcept.c b/sysdeps/i386/fpu/fesetexcept.c
index 6eeb5ab5b0..8c93264b0c 100644
--- a/sysdeps/i386/fpu/fesetexcept.c
+++ b/sysdeps/i386/fpu/fesetexcept.c
@@ -46,15 +46,20 @@ fesetexcept (int excepts)
       fenv_t temp;
 
       __asm__ ("fnstenv %0" : "=m" (*&temp));
+      /* Note: fnstenv masks all floating-point exceptions until the fldenv
+         or fldcw below.  */
 
       /* Clear or set relevant flags.  */
       temp.__status_word |= temp.__status_word & excepts;
 
       if ((~temp.__control_word) & excepts)
-        /* Setting the exception flags may trigger a trap (at the next
-           floating-point instruction, but that does not matter).
-           ISO C23 (7.6.4.4) does not allow it.  */
-        return -1;
+        {
+          /* Setting the exception flags may trigger a trap (at the next
+             floating-point instruction, but that does not matter).
+             ISO C23 § 7.6.4.4 does not allow it.  */
+          __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word));
+          return -1;
+        }
 
       /* Store the new status word (along with the rest of the environment).  */
       __asm__ ("fldenv %0" : : "m" (*&temp));

  parent reply	other threads:[~2023-10-30 15:21 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-24 11:37 [PATCH v2 0/3] Fix fesetexcept/fesetexceptflag on powerpc and x86 Adhemerval Zanella
2023-10-24 11:37 ` [PATCH v2 1/3] powerpc: Do not raise exception traps for fesetexcept/fesetexceptflag (BZ 30988) Adhemerval Zanella
2023-10-24 11:37 ` [PATCH v2 2/3] i686: Do not raise exception traps on fesetexcept (BZ 30989) Adhemerval Zanella
2023-10-24 13:43   ` Bruno Haible
2023-10-26 18:39     ` Adhemerval Zanella Netto
2023-10-30 15:21   ` Bruno Haible [this message]
2023-10-30 16:05     ` Adhemerval Zanella Netto
2023-10-24 11:37 ` [PATCH v2 3/3] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Adhemerval Zanella
2023-10-30 15:22   ` Bruno Haible

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