Re: [PATCH] x86: Optimize atomic_compare_and_exchange_[val|bool]_acq [BZ #28537]

[Arjan van de Ven <arjan@linux.intel.com>]

On 11/3/2021 10:26 AM, Oleh Derevenko wrote:
> Arjan
> 
>> What the patch does is check non-atomic first if the actual atomic operation has
> a chance of working. if it has a chance, the actual normal atomic
> operation is done as
> before. But if non-atomic read already tells you the cmpxchg has no
> chance to succeed, it errors
> out early.
> 
> The idea of atomic function is that they are intended to work fairly
> with any type of memory. In your case, the speculative reads for a
> cached device memory may result in cache access only and will prevent
> fetching memory updates from the device, thus making the reading
> thread "see" the change later than it could.


eh I am not sure I understand what you say since cmpxchg uses the exact same
cache protocol/etc to do its read...  it won't go to device memory either if
the cache line is anywhere in the cache hierarchy (including core-to-core transfers
in case another core has it in their caches)


(and cmpxchg on MMIO space has very very interesting and unexpected behavior. If folks remember
the "linux torches your e1000 eeprom" bug from some years ago, it came from that)