From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dog.elm.relay.mailchannels.net (dog.elm.relay.mailchannels.net [23.83.212.48]) by sourceware.org (Postfix) with ESMTPS id 3BD66384A40A for ; Mon, 21 Dec 2020 13:36:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3BD66384A40A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=gotplt.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=siddhesh@gotplt.org X-Sender-Id: dreamhost|x-authsender|siddhesh@gotplt.org Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 41001321C39; Mon, 21 Dec 2020 13:36:36 +0000 (UTC) Received: from pdx1-sub0-mail-a74.g.dreamhost.com (100-96-1-8.trex.outbound.svc.cluster.local [100.96.1.8]) (Authenticated sender: dreamhost) by relay.mailchannels.net (Postfix) with ESMTPA id D6830320FDF; Mon, 21 Dec 2020 13:36:35 +0000 (UTC) X-Sender-Id: dreamhost|x-authsender|siddhesh@gotplt.org Received: from pdx1-sub0-mail-a74.g.dreamhost.com (pop.dreamhost.com [64.90.62.162]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.18.11); Mon, 21 Dec 2020 13:36:36 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: dreamhost|x-authsender|siddhesh@gotplt.org X-MailChannels-Auth-Id: dreamhost X-Cooperative-Squirrel: 0c8f77d674443593_1608557796115_1329570423 X-MC-Loop-Signature: 1608557796115:2547983679 X-MC-Ingress-Time: 1608557796115 Received: from pdx1-sub0-mail-a74.g.dreamhost.com (localhost [127.0.0.1]) by pdx1-sub0-mail-a74.g.dreamhost.com (Postfix) with ESMTP id 4B85E830A1; Mon, 21 Dec 2020 05:36:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gotplt.org; h=subject:to :references:from:message-id:date:mime-version:in-reply-to :content-type:content-transfer-encoding; s=gotplt.org; bh=lk9f4a Mgd1wCwt23o4k9GsPCCzw=; b=T696n5ha0/xW6ExLTWVpaZDUtt2H0ZddU1ySFw cV7UW9ut1Ht5rHiN2JlLLa+JucochrHXieuuUNHI4xPWavHnh3o9WZTVCsXbqSmC OuDlPyRo3/PpwBifJldWuON4ntdve/5sT6pzv7QfZPFsn02MfeCv2oDhvA1Scu86 jSVXw= Received: from [192.168.1.111] (unknown [1.186.101.110]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: siddhesh@gotplt.org) by pdx1-sub0-mail-a74.g.dreamhost.com (Postfix) with ESMTPSA id 0CCAA7F73C; Mon, 21 Dec 2020 05:36:33 -0800 (PST) Subject: Re: [PATCH v4 5/6] aarch64: Add sysv specific enabling code for memory tagging To: Richard Earnshaw , libc-alpha@sourceware.org References: <20201218192957.11035-1-rearnsha@arm.com> <20201218192957.11035-6-rearnsha@arm.com> X-DH-BACKEND: pdx1-sub0-mail-a74 From: Siddhesh Poyarekar Message-ID: <5d84c02a-a165-9142-c508-1f87973dfe3d@gotplt.org> Date: Mon, 21 Dec 2020 19:06:29 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <20201218192957.11035-6-rearnsha@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, NICE_REPLY_A, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Dec 2020 13:36:50 -0000 On 12/19/20 12:59 AM, Richard Earnshaw via Libc-alpha wrote: > > Add various defines and stubs for enabling MTE on AArch64 sysv-like > systems such as Linux. The HWCAP feature bit is copied over in the > same way as other feature bits. Similarly we add a new wrapper header > for mman.h to define the PROT_MTE flag that can be used with mmap and > related functions. > > We add a new field to struct cpu_features that can be used, for > example, to check whether or not certain ifunc'd routines should be > bound to MTE-safe versions. > > Finally, if we detect that MTE should be enabled (ie via the glibc > tunable); we enable MTE during startup as required. > --- > sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h | 1 + > sysdeps/unix/sysv/linux/aarch64/bits/mman.h | 1 + > .../unix/sysv/linux/aarch64/cpu-features.c | 30 +++++++++++++++++++ > .../unix/sysv/linux/aarch64/cpu-features.h | 2 ++ > 4 files changed, 34 insertions(+) Looks OK to me. > diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h > index af90d8a626..389852f1d9 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h > +++ b/sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h > @@ -73,3 +73,4 @@ > #define HWCAP2_DGH (1 << 15) > #define HWCAP2_RNG (1 << 16) > #define HWCAP2_BTI (1 << 17) > +#define HWCAP2_MTE (1 << 18) > diff --git a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h > index ecae046344..c5ec0aa7d0 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/bits/mman.h > +++ b/sysdeps/unix/sysv/linux/aarch64/bits/mman.h > @@ -24,6 +24,7 @@ > arch/arm64/include/uapi/asm/mman.h. */ > > #define PROT_BTI 0x10 > +#define PROT_MTE 0x20 > > #include > > diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > index b9ab827aca..bd899c4b09 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > @@ -19,10 +19,17 @@ > #include > #include > #include > +#include > > #define DCZID_DZP_MASK (1 << 4) > #define DCZID_BS_MASK (0xf) > > +/* The maximal set of permitted tags that the MTE random tag generation > + instruction may use. We exclude tag 0 because a) we want to reserve > + that for the libc heap structures and b) because it makes it easier > + to see when pointer have been correctly tagged. */ > +#define MTE_ALLOWED_TAGS (0xfffe << PR_MTE_TAG_SHIFT) A Nice(TM) looking variable to mask the beautiful hex that should stay hidden ;) > + > #if HAVE_TUNABLES > struct cpu_list > { > @@ -86,4 +93,27 @@ init_cpu_features (struct cpu_features *cpu_features) > > /* Check if BTI is supported. */ > cpu_features->bti = GLRO (dl_hwcap2) & HWCAP2_BTI; > + > + /* Setup memory tagging support if the HW and kernel support it, and if > + the user has requested it. */ > + cpu_features->mte_state = 0; > + > +#ifdef USE_MTAG > +# if HAVE_TUNABLES > + int mte_state = TUNABLE_GET (glibc, mem, tagging, unsigned, 0); > + cpu_features->mte_state = (GLRO (dl_hwcap2) & HWCAP2_MTE) ? mte_state : 0; > + /* If we lack the MTE feature, disable the tunable, since it will > + otherwise cause instructions that won't run on this CPU to be used. */ > + TUNABLE_SET (glibc, mem, tagging, unsigned, cpu_features->mte_state); > +# endif > + > + if (cpu_features->mte_state & 2) > + __prctl (PR_SET_TAGGED_ADDR_CTRL, > + (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | MTE_ALLOWED_TAGS), > + 0, 0, 0); > + else if (cpu_features->mte_state) > + __prctl (PR_SET_TAGGED_ADDR_CTRL, > + (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_ASYNC | MTE_ALLOWED_TAGS), > + 0, 0, 0); > +#endif > } > diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h > index 00a4d0c8e7..bebf321a21 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h > +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h > @@ -70,6 +70,8 @@ struct cpu_features > uint64_t midr_el1; > unsigned zva_size; > bool bti; > + /* Currently, the GLIBC memory tagging tunable only defines 8 bits. */ > + uint8_t mte_state; > }; > > #endif /* _CPU_FEATURES_AARCH64_H */