From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTP id 6329A3857828 for ; Mon, 8 Mar 2021 22:28:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6329A3857828 Received: from mail-qv1-f70.google.com (mail-qv1-f70.google.com [209.85.219.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-36-gjL_XhP5PFG7Wc2tX0OEog-1; Mon, 08 Mar 2021 17:28:22 -0500 X-MC-Unique: gjL_XhP5PFG7Wc2tX0OEog-1 Received: by mail-qv1-f70.google.com with SMTP id u17so8757689qvq.23 for ; Mon, 08 Mar 2021 14:28:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=6OYSkEzAUjLLMTtGgdCPE92yxYQZL7RDMLCCw4VxJzY=; b=L1OF2xhYvOt/J1ijBKE5WsFiFqqKnBtpuvAa+KAGDr3+M3UVVn+qGIbXNS1QzmGi1t UOLD8iG9BeQxYcs72GprWEBuawUIE5h3e9bt6lwFjkJz2vByQwufrGacy6JwkJlp5hgA T74ge9x2CkuExw951/aTBhhukmNSmuRPRfNXJHyGG3lWoMn3FfUcIrUeJpsMH5MJ/mr8 GuGnxVPayMInEMqONE67fMdEwEvLrQPRDNjnq20dNrI+8uYfHLH7IKOSvUq8sO03c276 eKTKGGNNnAi5PArWQ0gd36tAcNobru7yw0rNSS8d7ilDS9rffOLo1Zn+AC4aQPlXlxF9 ITog== X-Gm-Message-State: AOAM533CQLPQb/xQlQZAJtEL9h+NVyZzkzjnl1O1TPUXe9NCrZ/D/qlp 2z5fXTzhGZ8qm/By4vCIRhsn1EGQ2SBZmuwOoRkViTgmw07DsG/fBoa1gG4SPoUZS+kQqRGfyPS /J9V/T6v582v/Dz7Vnd5W9UTwzx2Kf8+Ir6xDLCFrYT3V9OfVkRnA6PGkT+NJc1XCwzyAhQ== X-Received: by 2002:a37:9c92:: with SMTP id f140mr22218425qke.415.1615242501611; Mon, 08 Mar 2021 14:28:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJwnJ/1zlnWyC/vB+J9EjqmXRFJoD3J3dIaFxbOn1I1Qh7qNDvTIjm2wRB6/F0A2zKW+wCMdFg== X-Received: by 2002:a37:9c92:: with SMTP id f140mr22218408qke.415.1615242501338; Mon, 08 Mar 2021 14:28:21 -0800 (PST) Received: from [192.168.1.16] (198-84-214-74.cpe.teksavvy.com. [198.84.214.74]) by smtp.gmail.com with ESMTPSA id p12sm8480355qtw.27.2021.03.08.14.28.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Mar 2021 14:28:20 -0800 (PST) Subject: Re: [PATCH v2] x86_64: Update THREAD_SETMEM/THREAD_SETMEM_NC for IMM64 To: "H.J. Lu" Cc: GNU C Library References: <20210202191209.4036619-1-hjl.tools@gmail.com> From: Carlos O'Donell Organization: Red Hat Message-ID: <60a3a304-7f33-3727-a39a-5420d26d13a0@redhat.com> Date: Mon, 8 Mar 2021 17:28:19 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, NICE_REPLY_A, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Mar 2021 22:28:25 -0000 On 3/2/21 9:21 AM, H.J. Lu wrote: > On Mon, Mar 1, 2021 at 5:30 AM Carlos O'Donell wrote: >> >> On 2/2/21 2:12 PM, H.J. Lu via Libc-alpha wrote: >>> Since there is only "movq imm32s, mem64" and no "movq imm64, mem64", use >>> "movq reg64, mem64" to store 64-bit constant in TCB. >>> --- >>> sysdeps/x86_64/nptl/tls.h | 11 +++++++++++ >>> 1 file changed, 11 insertions(+) >>> >>> diff --git a/sysdeps/x86_64/nptl/tls.h b/sysdeps/x86_64/nptl/tls.h >>> index 20f0958780..9ec8703e45 100644 >>> --- a/sysdeps/x86_64/nptl/tls.h >>> +++ b/sysdeps/x86_64/nptl/tls.h >>> @@ -269,6 +269,11 @@ _Static_assert (offsetof (tcbhead_t, __glibc_unused2) == 0x80, >>> asm volatile ("movl %0,%%fs:%P1" : \ >>> : IMM_MODE (value), \ >>> "i" (offsetof (struct pthread, member))); \ >>> + else if (__builtin_constant_p (value) \ >>> + && (int64_t) (int32_t) (uintptr_t) value != (uintptr_t) value) \ >>> + asm volatile ("movq %0,%%fs:%P1" : \ >>> + : "r" (value), \ >>> + "i" (offsetof (struct pthread, member))); \ >> >> (1) Move conditional into 'else /* 8 */' section. >> >> The blocks of conditionals are predicated on the size of the member we are >> about to write to. >> >> In the block below... >> >>> else /* 8 */ \ >> >> ... here, we are about to write value into a member that is size 8. >> >> Your code changes the logical construction of the code, but in way that makes >> it more difficult to understand. >> >> We previously had: >> >> if (sizeof() == 1) >> >> else if (sizeof() == 4) >> >> else /* Assume 8 */ >> >> In your case we must already be in the 'else /* Assume 8 */' because otherwise >> we've be writing a 64-bit constant into a < 64-bit structure member. >> >> I think we should put your code into the else clause. >> >> 272 else /* 8 */ \ >> 273 { \ >> >> if (__builtin_constant_p (value) >> && ([the value is a >32-bit constant]) >> asm volatile ([use movq reg64, mem64]); >> else >> >> 274 asm volatile ("movq %q0,%%fs:%P1" : \ >> 275 : IMM_MODE ((uint64_t) cast_to_integer (value)), \ >> 276 "i" (offsetof (struct pthread, member))); \ >> 277 }}) >> >> (2) What if gcc can't prove it's constant? >> >> If the constant is >32-bit, but gcc can't prove it's constant, then don't we >> try to put a >32-bit constant into a 32-bit immediate? >> >> Shouldn't the code be structured the other way around? >> >> e.g. >> >> else /* 8 */ >> { >> if (__builtin_constant_p (value) >> && ([the value is a <= 32-bit constant]) >> asm volatile ([use movq imm32, mem64]); >> else >> asm volatile ([use movq reg64, mem64]); >> } >> >> This way the code is always correct? > > I changed it to > > if (!__builtin_constant_p (value) \ > || (int64_t) (int32_t) (uintptr_t) value == (uintptr_t) value) \ > asm volatile ("movq %q0,%%fs:%P1" : \ > : IMM_MODE ((uint64_t) cast_to_integer (value)), \ > "i" (offsetof (struct pthread, member))); \ > else \ > asm volatile ("movq %0,%%fs:%P1" : \ > : "r" (value), \ > "i" (offsetof (struct pthread, member))); \ > >>> { \ >>> asm volatile ("movq %q0,%%fs:%P1" : \ >>> @@ -294,6 +299,12 @@ _Static_assert (offsetof (tcbhead_t, __glibc_unused2) == 0x80, >>> : IMM_MODE (value), \ >>> "i" (offsetof (struct pthread, member[0])), \ >>> "r" (idx)); \ >>> + else if (__builtin_constant_p (value) \ >>> + && (int64_t) (int32_t) (uintptr_t) value != (uintptr_t) value) \ >>> + asm volatile ("movq %0,%%fs:%P1(,%q2,8)" : \ >>> + : "r" (value), \ >>> + "i" (offsetof (struct pthread, member[0])), \ >>> + "r" (idx)); \ >>> else /* 8 */ \ >>> { \ >>> asm volatile ("movq %q0,%%fs:%P1(,%q2,8)" : \ >>> >> > > Here is the v2 patch. OK for master? > > Thanks. > > From 4fbc9ab67933d662506a01658d4c81a922e50fdf Mon Sep 17 00:00:00 2001 > From: "H.J. Lu" > Date: Fri, 8 Jan 2021 15:38:14 -0800 > Subject: [PATCH v2] x86_64: Update THREAD_SETMEM/THREAD_SETMEM_NC for IMM64 > > Since there is only "movq imm32s, mem64" and no "movq imm64, mem64", use > "movq reg64, mem64" to store 64-bit constant. > --- > sysdeps/x86_64/nptl/tls.h | 27 ++++++++++++++++++++------- > 1 file changed, 20 insertions(+), 7 deletions(-) > > diff --git a/sysdeps/x86_64/nptl/tls.h b/sysdeps/x86_64/nptl/tls.h > index 20f0958780..0dbd66209c 100644 > --- a/sysdeps/x86_64/nptl/tls.h > +++ b/sysdeps/x86_64/nptl/tls.h > @@ -271,9 +271,15 @@ _Static_assert (offsetof (tcbhead_t, __glibc_unused2) == 0x80, > "i" (offsetof (struct pthread, member))); \ > else /* 8 */ \ > { \ > - asm volatile ("movq %q0,%%fs:%P1" : \ > - : IMM_MODE ((uint64_t) cast_to_integer (value)), \ > - "i" (offsetof (struct pthread, member))); \ > + if (!__builtin_constant_p (value) \ Whis is this a "!__builtin_constant_p?" I would have expected: if ([the value is a constant a therefore known quantity] || [it is a 32-bit value]) Perhaps a quick single line comment here explaining the conditionals would help? > + || (int64_t) (int32_t) (uintptr_t) value == (uintptr_t) value) \ > + asm volatile ("movq %q0,%%fs:%P1" : \ > + : IMM_MODE ((uint64_t) cast_to_integer (value)), \ > + "i" (offsetof (struct pthread, member))); \ > + else \ > + asm volatile ("movq %0,%%fs:%P1" : \ > + : "r" (value), \ > + "i" (offsetof (struct pthread, member))); \ > }}) > > > @@ -296,10 +302,17 @@ _Static_assert (offsetof (tcbhead_t, __glibc_unused2) == 0x80, > "r" (idx)); \ > else /* 8 */ \ > { \ > - asm volatile ("movq %q0,%%fs:%P1(,%q2,8)" : \ > - : IMM_MODE ((uint64_t) cast_to_integer (value)), \ > - "i" (offsetof (struct pthread, member[0])), \ > - "r" (idx)); \ > + if (!__builtin_constant_p (value) \ > + || (int64_t) (int32_t) (uintptr_t) value == (uintptr_t) value) \ > + asm volatile ("movq %q0,%%fs:%P1(,%q2,8)" : \ > + : IMM_MODE ((uint64_t) cast_to_integer (value)), \ > + "i" (offsetof (struct pthread, member[0])), \ > + "r" (idx)); \ > + else \ > + asm volatile ("movq %0,%%fs:%P1(,%q2,8)" : \ > + : "r" (value), \ > + "i" (offsetof (struct pthread, member[0])), \ > + "r" (idx)); \ > }}) > > > -- > 2.29.2 > -- Cheers, Carlos.