From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 102673858C27 for ; Wed, 20 Sep 2023 11:28:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 102673858C27 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=linux.vnet.ibm.com Received: from pps.filterd (m0353723.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38KAu5nm002306; Wed, 20 Sep 2023 11:28:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=F3yxfotr9cU5c+fDCs8awtheaAu8IIpKVWZEzrD+qt8=; b=tAYLp0Jy1zH+L/NeE/LlVfIp7PUTc8cFhA0LRrodrfjeXtF0Myo9CgkNgYneWdoO2+NB 48NyAc3Fp+emVV58W4+0UCw3jxIvWtKc5/3dY9vZRKHvHviOOYxXGtWpvBZ3Wo3ciV41 /J6xAAWs6b+DMeKNnG/DQC077rf+063HJksnCYHbsQQDBb+5wkYef7IOtVZnoMQpAO7/ TkCS6AWs6sFF/CTBMgkdzOs03Jt0GNLtoZCA2sgI7b0OYH6MCpmRwc86GxePlbcFHsJq kUyK/M8uF2ioqmCwHJDmE8IUxDXdD0dkIK88pOXivWTcGxFTV5QLL5mVXwf+ZrErm0Qe SA== Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3t7t3w0nkw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 11:28:10 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 38KBFVLK031219; Wed, 20 Sep 2023 11:28:10 GMT Received: from smtprelay02.wdc07v.mail.ibm.com ([172.16.1.69]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3t5r6kw3kw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 11:28:10 +0000 Received: from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com [10.39.53.229]) by smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 38KBS9PP66781530 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 20 Sep 2023 11:28:09 GMT Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 11EB358058; Wed, 20 Sep 2023 11:28:09 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BDBEA5805F; Wed, 20 Sep 2023 11:28:06 +0000 (GMT) Received: from [9.43.121.8] (unknown [9.43.121.8]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Wed, 20 Sep 2023 11:28:06 +0000 (GMT) Message-ID: <866d7459-b031-883b-f356-b05fa2e5ad71@linux.vnet.ibm.com> Date: Wed, 20 Sep 2023 16:58:04 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH] [powerpc] fegetenv_and_set_rn now uses the builtins provided by GCC. Content-Language: en-US To: Adhemerval Zanella Netto , Manjunath Matti , libc-alpha@sourceware.org Cc: rajis@linux.ibm.com, Carl Love References: <20230912082730.3951006-1-mmatti@linux.ibm.com> <526f2aac-a06c-d1cf-4c7b-1339846a1711@linaro.org> From: Manjunath S Matti In-Reply-To: <526f2aac-a06c-d1cf-4c7b-1339846a1711@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: J6oyjbPbzs1s-964uVifJo6AJAtUJOia X-Proofpoint-ORIG-GUID: J6oyjbPbzs1s-964uVifJo6AJAtUJOia X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_05,2023-09-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=766 spamscore=0 impostorscore=0 mlxscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 clxscore=1011 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200088 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,NICE_REPLY_A,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 12/09/23 6:57 pm, Adhemerval Zanella Netto wrote: > > On 12/09/23 05:27, Manjunath Matti wrote: >> On powerpc, SET_RESTORE_ROUND uses inline assembly to optimize the >> prologue get/save/set rounding mode operations for POWER9 and >> later by using 'mffscrn' where possible, this was introduced by >> commit f1c56cdff09f650ad721fae026eb6a3651631f3d. >> >> GCC version 14 onwards supports builtins as __builtin_set_fpscr_rn >> which now returns the FPSCR fields in a double. This feature is >> available on Power9 when the __SET_FPSCR_RN_RETURNS_FPSCR__ macro >> is defined along with __builtin_set_fpscr_rn enabled. >> GCC commit ef3bbc69d15707e4db6e2f198c621effb636cc26 adds >> this feature. >> >> Changes are done to use __builtin_set_fpscr_rn instead of mffscrn >> or mffscrni in __fe_mffscrn(rn). >> >> Suggested-by: Carl Love >> --- >> sysdeps/powerpc/fpu/fenv_libc.h | 23 ++++++++++++++++++++--- >> 1 file changed, 20 insertions(+), 3 deletions(-) >> >> diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h >> index fa5e1c697e..55484eb229 100644 >> --- a/sysdeps/powerpc/fpu/fenv_libc.h >> +++ b/sysdeps/powerpc/fpu/fenv_libc.h >> @@ -84,8 +84,15 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; >> __fr.fenv; \ >> }) >> >> +/* GCC version 14 onwards supports builtins as __builtin_set_fpscr_rn and >> + now returns the FPSCR fields in a double. This support is available >> + on Power9 when the __SET_FPSCR_RN_RETURNS_FPSCR__ macro is defined. >> + To retain backward compatibility with older GCC, we still retain the >> + old inline assembly implementation. */ >> +#if defined _ARCH_PWR9 && defined __SET_FPSCR_RN_RETURNS_FPSCR__ >> +#define fegetenv_and_set_rn(rn) __builtin_set_fpscr_rn (rn) >> +#elif defined _ARCH_PWR9 >> /* Like fegetenv_control, but also sets the rounding mode. */ >> -#ifdef _ARCH_PWR9 >> #define fegetenv_and_set_rn(rn) __fe_mffscrn (rn) >> #else >> /* 'mffscrn' will decode to 'mffs' on ARCH < 3_00, which is still necessary > I think the macro would be better defined as: > > #ifdef __SET_FPSCR_RN_RETURNS_FPSCR__ > # define __fe_mffscrn(rn) __builtin_set_fpscr_rn (rn) > #else > # define __fe_mffscrn(rn) [...] > #endif > > Then there is no need to redefine fegetenv_and_set_rn nor __fesetround_inline. So this is what you are asking me to do right ? --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -89,22 +89,11 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;     on Power9 when the __SET_FPSCR_RN_RETURNS_FPSCR__ macro is defined.     To retain backward compatibility with older GCC, we still retain the     old inline assembly implementation.  */ -#if defined _ARCH_PWR9 && defined __SET_FPSCR_RN_RETURNS_FPSCR__ +#ifdef __SET_FPSCR_RN_RETURNS_FPSCR__  #define fegetenv_and_set_rn(rn) __builtin_set_fpscr_rn (rn) -#elif defined _ARCH_PWR9 +#else  /* Like fegetenv_control, but also sets the rounding mode.  */  #define fegetenv_and_set_rn(rn) __fe_mffscrn (rn) -#else -/* 'mffscrn' will decode to 'mffs' on ARCH < 3_00, which is still necessary -   but not sufficient, because it does not set the rounding mode. -   Explicitly set the rounding mode when 'mffscrn' actually doesn't.  */ -#define fegetenv_and_set_rn(rn) \ -  ({register fenv_union_t __fr;                                                \ -    __fr.fenv = __fe_mffscrn (rn);                                     \ -    if (__glibc_unlikely (!(GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)))        \ -      __fesetround_inline (rn);                                                \ - __fr.fenv; \ -  })  #endif I was under the impression that the redefine of fegetenv_and_set_rn and __fesetround_inline was needed for architectures below POWE9, i.e POWER8, 7, etc. Please correct me if I am wrong. >> @@ -148,7 +155,12 @@ typedef union >> static inline int >> __fesetround_inline (int round) >> { >> -#ifdef _ARCH_PWR9 >> +/* GCC version 14 onwards supports builtins as __builtin_set_fpscr_rn and >> + now returns the FPSCR fields in a double. This support is available >> + on Power9 when the __SET_FPSCR_RN_RETURNS_FPSCR__ macro is defined. */ >> +#if defined _ARCH_PWR9 && defined __SET_FPSCR_RN_RETURNS_FPSCR__ >> + __builtin_set_fpscr_rn (round); >> +#elif defined _ARCH_PWR9 >> __fe_mffscrn (round); >> #else >> if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) >> @@ -178,7 +190,12 @@ __fesetround_inline (int round) >> static inline void >> __fesetround_inline_nocheck (const int round) >> { >> -#ifdef _ARCH_PWR9 >> +/* GCC version 14 onwards supports builtins as __builtin_set_fpscr_rn and >> + now returns the FPSCR fields in a double. This support is available >> + on Power9 when the __SET_FPSCR_RN_RETURNS_FPSCR__ macro is defined. */ >> +#if defined _ARCH_PWR9 && defined __SET_FPSCR_RN_RETURNS_FPSCR__ >> + __builtin_set_fpscr_rn (round); >> +#elif defined _ARCH_PWR9 >> __fe_mffscrn (round); >> #else >> if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) So the rest it OK ? I will update the patch with suggested changes.