From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id B0B373858D33 for ; Wed, 1 Feb 2023 16:42:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B0B373858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675269748; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=d+6B5YGpmLbVpvPhLZimot9lyg0RbZXkVMqq5RrfLp0=; b=E49uOQefY393XQcnttUqdWUsqdgOBkHyAOcj85h6z+H9mlacG5KBAzqupukfypmBQHe1h6 Zdp9KDpojAGkJsse5YedjFkfj/e7tSFAzHO9V/Na0fcQybKEo3uqxqCzm4c7WpaJNB6vDx M2oRWOgW3W1EX5hteGSamIXW27QN6tg= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-149-euhMG1D3NLuIl8s7TWrZmQ-1; Wed, 01 Feb 2023 11:42:26 -0500 X-MC-Unique: euhMG1D3NLuIl8s7TWrZmQ-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2481A18A6463; Wed, 1 Feb 2023 16:42:26 +0000 (UTC) Received: from oldenburg.str.redhat.com (unknown [10.39.194.58]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3E4FB112132C; Wed, 1 Feb 2023 16:42:25 +0000 (UTC) From: Florian Weimer To: Jeff Law via Libc-alpha Cc: Sergei Lewis , Jeff Law Subject: Re: [PATCH 2/2] riscv: vectorised mem* and str* functions References: <20230201095232.15942-1-slewis@rivosinc.com> <20230201095232.15942-2-slewis@rivosinc.com> <972db14d-390f-f79a-bc56-41afce041257@gmail.com> Date: Wed, 01 Feb 2023 17:42:23 +0100 In-Reply-To: <972db14d-390f-f79a-bc56-41afce041257@gmail.com> (Jeff Law via Libc-alpha's message of "Wed, 1 Feb 2023 08:33:13 -0700") Message-ID: <877cx1wd5c.fsf@oldenburg.str.redhat.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: * Jeff Law via Libc-alpha: > On 2/1/23 02:52, Sergei Lewis wrote: >> Initial implementations of memchr, memcmp, memcpy, memmove, memset, strchr, >> strcmp, strcpy, strlen, strncmp, strncpy, strnlen, strrchr, strspn >> targeting the riscv "V" extension, version 1.0 >> The vectorised implementations assume VLENB of at least 128 and at >> least 32 >> registers (as mandated by the "V" extension spec). They also assume that >> VLENB is a power of two which is no larger than the page size, and (as >> vectorised code in glibc for other platforms does) that it is safe to read >> past null terminators / buffer ends provided one does not cross a page >> boundary. >> Signed-off-by: Sergei Lewis >> --- >> sysdeps/riscv/rv64/rvv/Implies | 2 + >> sysdeps/riscv/rv64/rvv/memchr.S | 127 +++++++++++++++++++ >> sysdeps/riscv/rv64/rvv/memcmp.S | 93 ++++++++++++++ >> sysdeps/riscv/rv64/rvv/memcpy.S | 154 +++++++++++++++++++++++ >> sysdeps/riscv/rv64/rvv/memmove.c | 22 ++++ >> sysdeps/riscv/rv64/rvv/memset.S | 89 ++++++++++++++ >> sysdeps/riscv/rv64/rvv/strchr.S | 92 ++++++++++++++ >> sysdeps/riscv/rv64/rvv/strchrnul.c | 22 ++++ >> sysdeps/riscv/rv64/rvv/strcmp.S | 108 +++++++++++++++++ >> sysdeps/riscv/rv64/rvv/strcpy.S | 72 +++++++++++ >> sysdeps/riscv/rv64/rvv/strcspn.c | 22 ++++ >> sysdeps/riscv/rv64/rvv/strlen.S | 67 ++++++++++ >> sysdeps/riscv/rv64/rvv/strncmp.S | 104 ++++++++++++++++ >> sysdeps/riscv/rv64/rvv/strncpy.S | 96 +++++++++++++++ >> sysdeps/riscv/rv64/rvv/strnlen.S | 81 +++++++++++++ >> sysdeps/riscv/rv64/rvv/strrchr.S | 88 ++++++++++++++ >> sysdeps/riscv/rv64/rvv/strspn.S | 189 +++++++++++++++++++++++++++++ > Does this need to be revamped given the recent push to do more with > generic code and target specific hooks for mem* and str*? > > Shouldn't the implementations be in a multiarch directory? I would > fully expect we're going to need both a vector and scalar > implementation selected by an ifunc. I think most RISC-V GCC compilers won't have enabled IFUNC support? Looking at gcc/config.gcc in GCC 12, I see this: *-*-linux* | *-*-gnu*) case ${target} in aarch64*-* | arm*-* | i[34567]86-* | powerpc*-* | s390*-* | sparc*-* | x86_64-* | loongarch*-*) default_gnu_indirect_function=yes ;; esac But maybe that's not the right place to look at? We have an assembler hack to be able to still build IFUNC resolvers written in C, but I don't know if this works on RISC-V. Ideally the GCC defaults would change, too, and well before IFUNCs are in common use. Thanks, Florian