From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from albireo.enyo.de (albireo.enyo.de [37.24.231.21]) by sourceware.org (Postfix) with ESMTPS id C41A33857C7E for ; Fri, 26 Mar 2021 20:35:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org C41A33857C7E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=deneb.enyo.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=fw@deneb.enyo.de Received: from [172.17.203.2] (port=40449 helo=deneb.enyo.de) by albireo.enyo.de ([172.17.140.2]) with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) id 1lPtB0-00038H-F0; Fri, 26 Mar 2021 20:35:26 +0000 Received: from fw by deneb.enyo.de with local (Exim 4.92) (envelope-from ) id 1lPtB0-0008Aa-CB; Fri, 26 Mar 2021 21:35:26 +0100 From: Florian Weimer To: Andy Lutomirski Cc: "H. J. Lu" , X86 ML , LKML , "Bae\, Chang Seok" , "Carlos O'Donell" , Rich Felker , libc-alpha Subject: Re: Why does glibc use AVX-512? References: <87a6qqi064.fsf@mid.deneb.enyo.de> <87blb5d7zx.fsf@mid.deneb.enyo.de> Date: Fri, 26 Mar 2021 21:35:26 +0100 In-Reply-To: (Andy Lutomirski's message of "Fri, 26 Mar 2021 12:47:42 -0700") Message-ID: <877dltd569.fsf@mid.deneb.enyo.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Mar 2021 20:35:43 -0000 * Andy Lutomirski: > On Fri, Mar 26, 2021 at 12:34 PM Florian Weimer wrote: >> x86: Sporadic failures in tst-cpu-features-cpuinfo >> > > It's worth noting that recent microcode updates have make RTM > considerably less likely to actually work on many parts. It's > possible you should just disable it. :( Sorry, I'm not sure who should disable it. Let me sum up the situation: We have a request for a performance enhancement in glibc, so that applications can use it on server parts where RTM actually works. For CPUs that support AVX-512, we may be able to meet that with a change that uses the new 256-bit registers, t avoid the %xmm transition penalty. (This is the easy case, hopefully=E2=80=94there should= n't be any frequency issues associated with that, and if the kernel doesn't optimize the context switch today, that's a nonissue as well.) For CPUs that do not support AVX-512 but support RTM (and AVX2), we need a dynamic run-time check whether the string function is invoked in a transaction. In that case, we need to use VZEROALL instead of VZEROUPPER. (It's apparently too costly to issue VZEROALL unconditionally.) All this needs to work transparently without user intervention. We cannot require firmware upgrades to fix the incorrect RTM reporting issue (the bug I referenced). I think we can require software updates which tell glibc when to use RTM-enabled string functions if the dynamic selection does not work (either for performance reasons, or because of the RTM reporting bug). I want to avoid a situation where one in eight processes fail to work correctly because the CPUID checks ran on CPU 0, where RTM is reported as available, and then we trap when executing XTEST on other CPUs.