From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 234AC39A8009 for ; Fri, 16 Jul 2021 13:28:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 234AC39A8009 Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16GD4Cxu007023; Fri, 16 Jul 2021 09:28:16 -0400 Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0a-001b2d01.pphosted.com with ESMTP id 39twt8m5pd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Jul 2021 09:28:16 -0400 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 16GDC22A008471; Fri, 16 Jul 2021 13:28:15 GMT Received: from b03cxnp07027.gho.boulder.ibm.com (b03cxnp07027.gho.boulder.ibm.com [9.17.130.14]) by ppma03dal.us.ibm.com with ESMTP id 39rkgxwnum-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Jul 2021 13:28:15 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp07027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16GDSENl33030572 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 16 Jul 2021 13:28:14 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5AEC6C605D; Fri, 16 Jul 2021 13:28:14 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F3AE6C6063; Fri, 16 Jul 2021 13:28:13 +0000 (GMT) Received: from linux.ibm.com (unknown [9.211.73.116]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 16 Jul 2021 13:28:13 +0000 (GMT) From: Tulio Magno Quites Machado Filho To: Adhemerval Zanella , Anton Blanchard Cc: libc-alpha@sourceware.org Subject: Re: [PATCH 1/3] powerpc64: Replace some PPC_FEATURE_HAS_VSX with PPC_FEATURE_ARCH_2_06 In-Reply-To: <4241d750-5999-4a68-3c7f-faa1b3927577@linaro.org> References: <20210706105107.1866836-1-anton@ozlabs.org> <87k0m0l9rh.fsf@linux.ibm.com> <4241d750-5999-4a68-3c7f-faa1b3927577@linaro.org> User-Agent: Notmuch/0.32.1 (http://notmuchmail.org) Emacs/27.2 (x86_64-redhat-linux-gnu) Date: Fri, 16 Jul 2021 10:28:12 -0300 Message-ID: <878s26l76b.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: XeR0I8AmWl1lif-pJRMj8XlDI5xtuPp6 X-Proofpoint-ORIG-GUID: XeR0I8AmWl1lif-pJRMj8XlDI5xtuPp6 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-16_04:2021-07-16, 2021-07-16 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107160080 X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jul 2021 13:28:22 -0000 Adhemerval Zanella via Libc-alpha writes: > On 08/07/2021 19:29, Tulio Magno Quites Machado Filho via Libc-alpha wrote: >> I don't think we can replace PPC_FEATURE_HAS_VSX with PPC_FEATURE_ARCH_2_06 >> because it would cause issues similar to the ones fixed in patch 3/3, i.e. >> this function would run on a processor that implements the Power ISA 2.06 >> but does not implement Altivec. >> >> So, if testing for PPC_FEATURE_ARCH_2_06 is important, I think it has to test >> for: >> >> (hwcap & PPC_FEATURE_ARCH_2_06 && hwcap & PPC_FEATURE_HAS_ALTIVEC) >> >> However, VSX was introduced by Power ISA 2.06. So, PPC_FEATURE_HAS_VSX >> implies PPC_FEATURE_ARCH_2_06. PPC_FEATURE_HAS_VSX also implies >> PPC_FEATURE_HAS_ALTIVEC. >> The change would only make a difference if a processor implements both Power >> ISA 2.06 and Altivec, but does not implement VSX. >> >> Am I missing anything? > > My understanding is the selection change done for this patch is to enable > routines that do *not* use vectorized instructions (either VSX or altivec) > on a CPU that does have isa 2.06 (to use cmpb for instance). Yes. My previous comment would only make sense for functions using Altivec, but these functions are not. I'm sorry. > That's why > I suggested that we should in fact rename them and also maybe move to > a different folder than 'power7' to something more meaningful (for instance > __memchr_isa206 or something). I don't have a strong opinion on this. LGTM either way. >> Another important point is to keep the tests in the IFUNC resolvers in sync >> with sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c >> Otherwise, glibc tests and benchtests may not execute correctly. Heads up this paragraph is still valid. -- Tulio Magno