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From: Florian Weimer <fw@deneb.enyo.de>
To: "sajan.karumanchi--- via Libc-alpha" <libc-alpha@sourceware.org>
Cc: carlos@redhat.com,  fweimer@redhat.com,
	 sajan.karumanchi@gmail.com,
	Sajan Karumanchi <sajan.karumanchi@amd.com>,
	premachandra.mallappa@amd.com
Subject: Re: [PATCH] x86: Fix for cache computation on AMD legacy cpus.
Date: Fri, 02 Jun 2023 18:51:16 +0200	[thread overview]
Message-ID: <87a5xhq03f.fsf@mid.deneb.enyo.de> (raw)
In-Reply-To: <20230602131907.1375745-1-sajan.karumanchi@amd.com> (sajan karumanchi's message of "Fri, 2 Jun 2023 13:19:07 +0000")

* sajan karumanchi:

> From: Sajan Karumanchi <sajan.karumanchi@amd.com>
>
> Some legacy AMD CPUs and hypervisors have the _cpuid_ '0x8000_001D'
> set to Zero, thus resulting in zeroed-out computed cache values.
> This patch reintroduces the old way of cache computation as a
> failsafe option to handle these exceptions.
>
> Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>

Thanks.  On “AMD Turion(tm) II Neo N40L Dual-Core Processor”, this
fixes the regression.  The reported cache sizes are identical.

There's still one remaining issue (not a regression):

x86.cpu_features.level4_cache_size=0xffffffffffffffff

I think this should be zero if there is no L4 cache.

I'm going to test more machines early next week.

  reply	other threads:[~2023-06-02 16:51 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-02 13:19 sajan.karumanchi
2023-06-02 16:51 ` Florian Weimer [this message]
2023-06-05 18:59 ` Florian Weimer
2023-06-06 13:42   ` Karumanchi, Sajan
2023-08-01 15:20 ` PATCH v2] " sajan.karumanchi
2023-08-01 15:20   ` [PATCH " sajan.karumanchi
2023-08-02  1:36     ` Sergio Durigan Junior
2023-08-02  6:43     ` Florian Weimer

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