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From: Florian Weimer <fweimer@redhat.com>
To: "Karumanchi, Sajan" <Sajan.Karumanchi@amd.com>
Cc: "libc-alpha@sourceware.org" <libc-alpha@sourceware.org>,
  "carlos@redhat.com" <carlos@redhat.com>,  "Mallappa, Premachandra"
 <Premachandra.Mallappa@amd.com>
Subject: Re: [PATCH v1] x86: Cache computation for AMD architecture.
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Date: Mon, 08 May 2023 19:06:29 +0200
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	(Sajan Karumanchi's message of "Wed, 18 Jan 2023 07:39:42 +0000")
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I'm sorry to report this new cache size computation approach is not
compatible with older AMD CPUs.  Some existing hypervisors set these
CPUID values to zero while still identifying these CPUs as AMD.  I filed
a new bug to track this regression:

  New AMD cache size computation logic does not work for some CPUs,
  hypervisors
  <https://sourceware.org/bugzilla/show_bug.cgi?id=30428>

It looks like we need to keep the old way of doing things.
Would you be able to work on a new patch?

I'm also going to file a separate bug, suggesting that we deselect
string functions that require cache size information if this information
is not available (mostly due to hypervisor masking).  But that's a
different issue.

Thanks,
Florian