From: "Tulio Magno Quites Machado Filho" <tuliom@linux.vnet.ibm.com>
To: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>,
libc-alpha@sourceware.org
Subject: Re: [PATCH] powerpc: Use aligned stores in memset
Date: Mon, 21 Aug 2017 02:20:00 -0000 [thread overview]
Message-ID: <87y3qdslu3.fsf@linux.vnet.ibm.com> (raw)
In-Reply-To: <1503033107-20047-1-git-send-email-raji@linux.vnet.ibm.com>
Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> writes:
> The powerpc hardware does not allow unaligned accesses on non cacheable
> memory. This patch avoids misaligned stores for sizes less than 8 in
> memset to avoid such cases. Tested on powerpc64 and powerpc64le.
This commit message is misleading. I think it's necessary to improve with:
1. Remove the first line.
2. Mention the performance impact and what causes it.
3. Reference the section "3.1.4.2 Alignment Interrupts" of the "POWER8
Processor User's Manual for the Single-Chip Module", which describes
this behavior.
4. Mention which kind of programs are affected by the old behavior.
> 2017-08-17 Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
>
> * sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
> for unaligned inputs if size is less than 8.
> ---
> sysdeps/powerpc/powerpc64/power8/memset.S | 68 ++++++++++++++++++++++++++++++-
> 1 file changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/sysdeps/powerpc/powerpc64/power8/memset.S b/sysdeps/powerpc/powerpc64/power8/memset.S
> index 7ad3bb1b00..504bab0841 100644
> --- a/sysdeps/powerpc/powerpc64/power8/memset.S
> +++ b/sysdeps/powerpc/powerpc64/power8/memset.S
> @@ -377,7 +377,8 @@ L(write_LT_32):
> subf r5,r0,r5
>
> 2: bf 30,1f
> - sth r4,0(r10)
> + stb r4,0(r10)
> + stb r4,1(r10)
Needs a comment to prevent future mistakes in the future.
> @@ -437,11 +438,74 @@ L(tail5):
> /* Handles copies of 0~8 bytes. */
> .align 4
> L(write_LE_8):
> - bne cr6,L(tail4)
> + /* Use stb instead of sth which is safe for
> + both aligned and unaligned inputs. */
I don't think "safe" is the correct term. What about this?
Use stb instead of sth because it doesn't generate alignment interrupts
on cache-inhibited storage.
> + bne cr6,L(LE7_tail4)
> + /* If input is word aligned, use stw, Else use stb. */
s/Else/else/
--
Tulio Magno
prev parent reply other threads:[~2017-08-21 2:20 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-18 5:13 Rajalakshmi Srinivasaraghavan
2017-08-18 6:21 ` Florian Weimer
2017-08-18 6:51 ` Rajalakshmi Srinivasaraghavan
2017-08-18 9:10 ` Florian Weimer
2017-08-18 12:13 ` Adhemerval Zanella
2017-09-12 10:30 ` Florian Weimer
2017-09-12 12:18 ` Zack Weinberg
2017-09-12 13:57 ` Steven Munroe
2017-09-12 14:37 ` Joseph Myers
2017-09-12 15:06 ` Zack Weinberg
2017-09-12 17:09 ` Florian Weimer
2017-09-12 13:38 ` Steven Munroe
2017-09-12 14:08 ` Florian Weimer
2017-09-12 14:16 ` Steven Munroe
2017-09-12 17:04 ` Florian Weimer
2017-09-12 19:21 ` Steven Munroe
2017-09-12 19:45 ` Florian Weimer
2017-09-12 20:25 ` Steven Munroe
2017-09-13 13:12 ` Tulio Magno Quites Machado Filho
2017-09-18 13:54 ` Florian Weimer
2017-10-03 18:29 ` Adhemerval Zanella
2017-10-05 12:13 ` Rajalakshmi Srinivasaraghavan
2017-11-08 18:52 ` Tulio Magno Quites Machado Filho
2017-12-08 19:52 ` [PATCHv2] powerpc: POWER8 memcpy optimization for cached memory Tulio Magno Quites Machado Filho
2017-12-08 20:06 ` Florian Weimer
2017-12-11 12:44 ` Tulio Magno Quites Machado Filho
2017-12-11 20:09 ` Adhemerval Zanella
2017-12-10 7:11 ` Rajalakshmi Srinivasaraghavan
2017-12-11 19:48 ` Tulio Magno Quites Machado Filho
2017-08-18 6:25 ` [PATCH] powerpc: Use aligned stores in memset Andrew Pinski
2017-08-21 2:20 ` Tulio Magno Quites Machado Filho [this message]
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