From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80044.outbound.protection.outlook.com [40.107.8.44]) by sourceware.org (Postfix) with ESMTPS id 5C4FF3858C50 for ; Thu, 28 Jul 2022 14:28:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5C4FF3858C50 ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=IPoetAi/XrAP7rgwVWpADcJF0iHwj21JWPfzsfKYIlHW7/2uoqjgnaFpRkA6+setsxp4YxYgDPciKxS7oWVhl1WocySFr6+tV3DTMkLMuEVZwFIVEn9pegZq0uYMlxvQ66nNyqHzY8J5PRoOXXLCMra73OzF/Vvdl8SC0IHs9Tapsgb5Kje15Z1QG/OqwEvMIkuFkt2XWBK20k1I7tSIcSFhxKbgfOzJs8G8lmx9j8qYnGw065dre6Sz/2Af8VCmZ4XOV8t26IxFNaCnnlPZAGaiG+5KPNccn3YUIMXEHCPoRcFgnxIOMGAa7dpXhMJYHevQaIuYniu9uNfvjhXYwg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IRovgP9yI3HNUg+oBdaHFuZZgTEhfrzFfgFn22N1Meg=; b=kYrZrzuzC2yU6xp0hO4Dme1Xjod+Y74Klk07tA83lJ08wOWzvku+dnMK80ViUGZVmxHZh6EcQ2Xj2w+9CJ7xrAqAsOGkcIsh99mTMENhHbB5rM4NLUHsDvP5viezuXk/pGem3ulfsa3oKys5pE6hrdFfp9fz9D7tj49qgVAqPU1P1cQFaY9GBLQnVNkOmKh5L5LImnMJqlaUINuIQQQKcB9dVTqzZJaLF/fJAXuhapn3TnvL5bh25xvSP3BowlIuXxNZ2EQPCHTGhKad2kIa4bSpuLzRrFoOcjf8jtdll0Vs8WVR8UPsYzYI7tsK3zIwSexrPXDg5LnHj6U7tVX98A== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) Received: from DB9PR05CA0005.eurprd05.prod.outlook.com (2603:10a6:10:1da::10) by DBBPR08MB5961.eurprd08.prod.outlook.com (2603:10a6:10:203::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5458.20; Thu, 28 Jul 2022 14:28:04 +0000 Received: from DBAEUR03FT022.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:1da:cafe::a) by DB9PR05CA0005.outlook.office365.com (2603:10a6:10:1da::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5482.10 via Frontend Transport; Thu, 28 Jul 2022 14:28:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT022.mail.protection.outlook.com (100.127.142.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5482.12 via Frontend Transport; Thu, 28 Jul 2022 14:28:04 +0000 Received: ("Tessian outbound fa99bf31ee7d:v123"); Thu, 28 Jul 2022 14:28:04 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 874dd59488b77e1e X-CR-MTA-TID: 64aa7808 Received: from d8a32a9b740e.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 83328EBE-6624-47A5-9D50-98075B426A87.1; Thu, 28 Jul 2022 14:27:58 +0000 Received: from EUR01-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id d8a32a9b740e.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 28 Jul 2022 14:27:58 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lH8ZCAsYj4f22J9zeSug6tM0w4CoSkT/41p+r9WdHoZKLPrmbgDh7K+YTJQngk4V95JGZzMndVLac3MzSY1b3Aw9yTVWnq2Ktb7iKISny+SSZ5wBIMt4FY76abu8ajxNofZpl6HtPnSkr1xIbQBm4KQjTTqvRxw/sCByHEZkYCOs8e0n/yDLg7B2XmYbcQciW8dABQPkBAvPkVkveYqdll/i9z7/TOeWbULiddsZ/BsNeog0xqmsMqNyoiCAvGG5VeRikx3/pd7D6AsOl5wNfttyFIy9Yig9US7dIsAPmBj9Q8BcsfDxVeAcY9Hi3fe+5Nu2WTRPF0QJRnb9mHSf0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IRovgP9yI3HNUg+oBdaHFuZZgTEhfrzFfgFn22N1Meg=; b=V2JvrEUlhDgYgB+Jr7O5d1/AERyYvjn7UzdTTEvJYLx66ilC6Sd7bipItZrA4lOO3K9J6Y79m6FEQ48wDatQ7mmtbBmAWVQWIvFUO0PnGZMHlkjC66OJH2XI/t1aNBzwrgTjXUq/k/dw1jxFWDVTQPO1TKTxl/Qeil8W1a1/t7rmiwLHaWlg1wiO5jJo3ML0ryO6VyU6ZxmMFfkT+9LborB+0lm9i6eYt5ajvN5BmLhdM+FE3+wyLGzr9y/e5A3T/C/iYh5TFqzMswrAydb0O9CRkuo8KNXTCFDzLWs568MP6KN68BvvET4ASU7hTaDNVbAKCMn6M5bG4BD3hjLIMA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Received: from AM5PR0801MB1668.eurprd08.prod.outlook.com (2603:10a6:203:3c::14) by DB6PR08MB2631.eurprd08.prod.outlook.com (2603:10a6:6:23::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5482.10; Thu, 28 Jul 2022 14:27:55 +0000 Received: from AM5PR0801MB1668.eurprd08.prod.outlook.com ([fe80::845f:5b9c:410a:f581]) by AM5PR0801MB1668.eurprd08.prod.outlook.com ([fe80::845f:5b9c:410a:f581%5]) with mapi id 15.20.5482.011; Thu, 28 Jul 2022 14:27:54 +0000 From: Wilco Dijkstra To: 'GNU C Library' Subject: [PATCH] Use atomic_thread_fence Thread-Topic: [PATCH] Use atomic_thread_fence Thread-Index: AQHYoo3ov0wgqXTG0kKR3cBSV10cOg== Date: Thu, 28 Jul 2022 14:27:53 +0000 Message-ID: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-MS-Office365-Filtering-Correlation-Id: ee028528-eded-4906-6b0b-08da70a56236 x-ms-traffictypediagnostic: DB6PR08MB2631:EE_|DBAEUR03FT022:EE_|DBBPR08MB5961:EE_ x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: JHguxn5ec1/E0RMiD4N1j5m0sB87x2BoYezcincUxUJqsLv+3Tz7AWIwM6OMadqR0/Bz1N4VutSSaQRSr3Rn+MYrNdH/gDs56dO9lH216fhC1YFo09jw8at25khMIlj7XZnh6hVflHjDMeik9I9XXxsj7eXCyyYqEOlBWY+ahLgn6boxGtaJVuRsX9fOkm4g86aJGn4Ko8PclocnZXXVeRNu7Nh7NsrH7aeHyc2Z+vwuR1I497xlcDBSsb4GDAH8PgQZYnWSgWJA1uZY0yuPuuYyNSManuFBcdzCq1/yXSVm2VmTg/dSZ2eumly4k+xeV4viSHwvb7I4XnlXJO0kA9HPa3uqBxJDqeRmVdtEUc0LfUtugEHB29ahnKjQwaSUuCCOY71da8rry1ii7neP3pfR4mVqZY4DKDjCii5IpMLTP29ZkuBUX+G882GdAUISjxSAnBvfTTjmawp/Z5WEHk4Sm9fCcHTX15ufK4R1+DiYXn1gFOb5nGXo8oxrNg0UGsamJ6L8AbgC03zhRJ0e8OyQzGYInFIO7LrRvfBUo4Cqhqb4L36iBGIi+o1mp2g+SOKndSzwHMNNLGmmPZCDyPx4L7dNGJehqyKZxO5953aTJiReWcHrcrxCH/tBv4OOp3sN5HCXzbsMwUW7oFNCjNyxFvhCWq3MKqTKaCDtVDr9eajskkzNsSqa/0ClniklDYWq0a24f0pOECg0AG218dkPynEsbXA3J3aQyYOPzjKEP6CRMVSxejcD0iZSy9TY8maYz3UyvMw5OXWinMi/sPM78utcxYff1p/+nE/NIURQ0gJpyTxUH/q23t8dam89mVxP1issJ5Nl7Vbdayl8CNsDVfhEsSWiv7PnpI1XqKeZVMQZK27GnQZA+v8oRvBE X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM5PR0801MB1668.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(4636009)(366004)(39860400002)(396003)(136003)(346002)(376002)(122000001)(316002)(71200400001)(86362001)(38100700002)(33656002)(41300700001)(186003)(26005)(6506007)(7696005)(6916009)(478600001)(9686003)(30864003)(66446008)(8676002)(2906002)(55016003)(5660300002)(52536014)(66476007)(64756008)(76116006)(66946007)(91956017)(66556008)(8936002)(83380400001)(38070700005)(21314003)(2004002)(579004)(559001); DIR:OUT; SFP:1101; Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR08MB2631 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT022.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: cc7984a0-9c42-47c3-cb81-08da70a55b72 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: c1nL2nIVDJwcxyXcCc4eUaSnYSroARdIoqhiBXQ3SIZ/pZYrSaoiB6VbOnC0DOFhww/zL/Adrja0qcYHkwNbUeemwKMRKMy64oCd1FWqktIgmF3nbrOyYLUzvllFqnowfaqGaYCuYoXxXpXw4/SAki8sHFkX1GMbbqh3Ip8/NaSfSNGqlW6ZTdobvWGbA1YVslYAk4xEU/yx830g0h7zNQRB3OamgEP1AgzcxvLjka3leYIM2H+bHh13ANKgqMq46h2WKLaBCAN/i9i8IC9vD0X5t8Xpy7cyXiLKluYI5d1VlW4Qqd37aPohwuEKHwRQeBm2ObKsnBSo8E2YH52ZWxv1mFjbGC2ztoNlbwNnFGN686tTfkwcUHi61aEdD7oDZQgEIvTo9F8MOvuJiDOyFlpH9NaqMAbveuMlrjlQQOnOKT4DAiwp9ZrX7BP964XAHn4HJql2SKl0izalDNogR/XyzkmJTSvHi0B08E/nd6IxJ8gP53pw8hM590P3Th9Lo6n/Yaaqkji/tcAS8mV4xg16syhEchm1pL7JkntwX953w8JCssT2z4rSQDtgeyTJSx2M05l+XZNNAlpalITQHyEbyPWyCnXF7Ao+sWTEl/0NBLc6HIhtjZKnkdi/N/U2Q1IwI+0ZGuidqE/iH8pVKgL73PP0UG3z+A8M/aSciq6wXT7nKkMSDUsPkEQtq7KDRAhyWSlA68D51Cg3sLYPD7wpKmmj6Kn15+IJHhtEkRzF1cMjeyOM5gc+e/vH/l8OYBHJWsODQkIPr55LdUMQKdtaWfbtlKXq1nGZGpy6yRGzX9Nk0g8wsjvA2REaBfReisRIm5SR/0d+d6XDSwY4WpFBZvOnf3IBOCiZCFrcRVC40lNDBvlEw19Dctq7B4/W X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230016)(4636009)(376002)(346002)(396003)(136003)(39860400002)(46966006)(40470700004)(36840700001)(8936002)(7696005)(6506007)(316002)(40480700001)(5660300002)(36860700001)(82310400005)(478600001)(40460700003)(55016003)(33656002)(2906002)(70586007)(86362001)(26005)(70206006)(9686003)(81166007)(336012)(186003)(82740400003)(356005)(47076005)(52536014)(30864003)(6916009)(83380400001)(8676002)(41300700001)(21314003)(2004002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2022 14:28:04.5838 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee028528-eded-4906-6b0b-08da70a56236 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT022.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB5961 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jul 2022 14:28:11 -0000 Replace atomic barriers based on sync primitives with atomic_thread_fence.= =0A= Many uses appear suspect and in the future fixing these to use load_acquire= =0A= or store_release would be useful.=0A= =0A= Passes regress on AArch64 and buildmanyglibc.=0A= =0A= ---=0A= =0A= diff --git a/crypt/crypt_util.c b/crypt/crypt_util.c=0A= index be925e3484e65d2180e07915f5d91b47f6b96393..a8c2b26ed13c27804a9465f2a54= caa09aaec3814 100644=0A= --- a/crypt/crypt_util.c=0A= +++ b/crypt/crypt_util.c=0A= @@ -453,14 +453,14 @@ __init_des_r (struct crypt_data * __restrict __data)= =0A= efp[comes_from_word][word_value][o_long] |=3D mask2;=0A= }=0A= }=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= small_tables_initialized =3D 1;=0A= #ifdef __GNU_LIBRARY__=0A= small_tables_done:=0A= __libc_lock_unlock(_ufc_tables_lock);=0A= #endif=0A= } else=0A= - atomic_read_barrier ();=0A= + atomic_thread_fence_acquire ();=0A= =0A= /*=0A= * Create the sb tables:=0A= diff --git a/elf/dl-deps.c b/elf/dl-deps.c=0A= index 06005a0cc8686cc7e63cd8e1b1e7deda01fe6688..11b3fda5fdeb3830d3d5a003108= 4b43847444e04 100644=0A= --- a/elf/dl-deps.c=0A= +++ b/elf/dl-deps.c=0A= @@ -430,7 +430,7 @@ _dl_map_object_deps (struct link_map *map,=0A= memcpy (&l_initfini[1], needed, nneeded * sizeof needed[0]);=0A= memcpy (&l_initfini[nneeded + 1], l_initfini,=0A= nneeded * sizeof needed[0]);=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= l->l_initfini =3D l_initfini;=0A= l->l_free_initfini =3D 1;=0A= }=0A= @@ -555,12 +555,12 @@ _dl_map_object_deps (struct link_map *map,=0A= =0A= /* Terminate the list of dependencies. */=0A= l_initfini[nlist] =3D NULL;=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= map->l_initfini =3D l_initfini;=0A= map->l_free_initfini =3D 1;=0A= if (l_reldeps !=3D NULL)=0A= {=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= void *old_l_reldeps =3D map->l_reldeps;=0A= map->l_reldeps =3D l_reldeps;=0A= _dl_scope_free (old_l_reldeps);=0A= diff --git a/elf/dl-lookup.c b/elf/dl-lookup.c=0A= index 02c63a7062b2be0f37a412160fdb2b3468cc70cf..894d3e7db198a2a08940e9a1d82= c345b0e0343a0 100644=0A= --- a/elf/dl-lookup.c=0A= +++ b/elf/dl-lookup.c=0A= @@ -695,7 +695,7 @@ marking %s [%lu] as NODELETE due to memory allocation f= ailure\n",=0A= l_reldepsact * sizeof (struct link_map *));=0A= newp->list[l_reldepsact] =3D map;=0A= newp->act =3D l_reldepsact + 1;=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= void *old =3D undef_map->l_reldeps;=0A= undef_map->l_reldeps =3D newp;=0A= undef_map->l_reldepsmax =3D max;=0A= @@ -706,7 +706,7 @@ marking %s [%lu] as NODELETE due to memory allocation f= ailure\n",=0A= else=0A= {=0A= undef_map->l_reldeps->list[l_reldepsact] =3D map;=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= undef_map->l_reldeps->act =3D l_reldepsact + 1;=0A= }=0A= =0A= diff --git a/elf/dl-open.c b/elf/dl-open.c=0A= index a23e65926bcfe797f06f8b4175f65040f4547a05..ba77f4b774cae69c382bceb6599= 936664203ef05 100644=0A= --- a/elf/dl-open.c=0A= +++ b/elf/dl-open.c=0A= @@ -202,7 +202,7 @@ add_to_global_update (struct link_map *new)=0A= assert (added <=3D ns->_ns_global_scope_pending_adds);=0A= ns->_ns_global_scope_pending_adds -=3D added;=0A= =0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= ns->_ns_main_searchlist->r_nlist =3D new_nlist;=0A= }=0A= =0A= @@ -342,7 +342,7 @@ update_scopes (struct link_map *new)=0A= might use the new last element and then use the garbage=0A= at offset IDX+1. */=0A= imap->l_scope[cnt + 1] =3D NULL;=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= imap->l_scope[cnt] =3D &new->l_searchlist;=0A= =0A= from_scope =3D cnt;=0A= diff --git a/include/atomic.h b/include/atomic.h=0A= index 8eb56362ba18eb4836070930d5f2e769fb6a0a1e..dfe60ddb27fed1a06fb4967968e= 7d5d64de2f9c3 100644=0A= --- a/include/atomic.h=0A= +++ b/include/atomic.h=0A= @@ -104,21 +104,6 @@=0A= #endif=0A= =0A= =0A= -#ifndef atomic_full_barrier=0A= -# define atomic_full_barrier() __sync_synchronize()=0A= -#endif=0A= -=0A= -=0A= -#ifndef atomic_read_barrier=0A= -# define atomic_read_barrier() atomic_full_barrier ()=0A= -#endif=0A= -=0A= -=0A= -#ifndef atomic_write_barrier=0A= -# define atomic_write_barrier() atomic_full_barrier ()=0A= -#endif=0A= -=0A= -=0A= /* This is equal to 1 iff the architecture supports 64b atomic operations.= */=0A= #ifndef __HAVE_64B_ATOMICS=0A= #error Unable to determine if 64-bit atomics are present.=0A= diff --git a/include/list.h b/include/list.h=0A= index 7bea2c50a3759c0c8640971eff1e80874e3b543f..31a8a93fa2491b38c368b9e07dd= 65c473e4eb19f 100644=0A= --- a/include/list.h=0A= +++ b/include/list.h=0A= @@ -43,7 +43,7 @@ list_add (list_t *newp, list_t *head)=0A= newp->next =3D head->next;=0A= newp->prev =3D head;=0A= head->next->prev =3D newp;=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= head->next =3D newp;=0A= }=0A= =0A= diff --git a/malloc/arena.c b/malloc/arena.c=0A= index 7c74a18381a4be5fe6bcb94b38a62dbfa6b674f4..3ef52ade3aeaaba6bb5e5d4e700= 24202e0dc162b 100644=0A= --- a/malloc/arena.c=0A= +++ b/malloc/arena.c=0A= @@ -111,7 +111,7 @@ static mstate free_list;=0A= malloc_state objects.=0A= =0A= Read access to the next member is supposed to synchronize with the=0A= - atomic_write_barrier and the write to the next member in=0A= + atomic_thread_fence_release and the write to the next member in=0A= _int_new_arena. This suffers from data races; see the FIXME=0A= comments in _int_new_arena and reused_arena.=0A= =0A= @@ -778,7 +778,7 @@ _int_new_arena (size_t size)=0A= /* FIXME: The barrier is an attempt to synchronize with read access=0A= in reused_arena, which does not acquire list_lock while=0A= traversing the list. */=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= main_arena.next =3D a;=0A= =0A= __libc_lock_unlock (list_lock);=0A= diff --git a/manual/llio.texi b/manual/llio.texi=0A= index 1b801ee817db2935d8866894be23ffa516690ca3..eb8711a0f8e28281baf68206b78= 91f16f662de0b 100644=0A= --- a/manual/llio.texi=0A= +++ b/manual/llio.texi=0A= @@ -2543,14 +2543,14 @@ aiocb64}, since the LFS transparently replaces the = old interface.=0A= @c deallocate_stack @asulock @ascuheap @aculock @acsmem=0A= @c lll_lock (state_cache_lock) @asulock @aculock=0A= @c stack_list_del ok=0A= -@c atomic_write_barrier ok=0A= +@c atomic_thread_fence_release ok=0A= @c list_del ok=0A= -@c atomic_write_barrier ok=0A= +@c atomic_thread_fence_release ok=0A= @c queue_stack @ascuheap @acsmem=0A= @c stack_list_add ok=0A= -@c atomic_write_barrier ok=0A= +@c atomic_thread_fence_release ok=0A= @c list_add ok=0A= -@c atomic_write_barrier ok=0A= +@c atomic_thread_fence_release ok=0A= @c free_stacks @ascuheap @acsmem=0A= @c list_for_each_prev_safe ok=0A= @c list_entry ok=0A= diff --git a/manual/memory.texi b/manual/memory.texi=0A= index 110e736a64c667988f4ca2fe92deb409225a4a88..2dfd09ea4aace004067e2e1d51c= 9e1292d1f7452 100644=0A= --- a/manual/memory.texi=0A= +++ b/manual/memory.texi=0A= @@ -395,7 +395,7 @@ this function is in @file{stdlib.h}.=0A= @c mutex_init ok=0A= @c mutex_lock (just-created mutex) ok, returns locked=0A= @c mutex_lock (list_lock) dup @asulock @aculock=0A= -@c atomic_write_barrier ok=0A= +@c atomic_thread_fence_release ok=0A= @c mutex_unlock (list_lock) @aculock=0A= @c atomic_fetch_add_relaxed ok=0A= @c reused_arena @asulock @aculock=0A= diff --git a/manual/startup.texi b/manual/startup.texi=0A= index 9bf24123f562f75ba27a4770c69147e003b94755..4c7c2976a92d772909203bca028= 347e8d798b2d7 100644=0A= --- a/manual/startup.texi=0A= +++ b/manual/startup.texi=0A= @@ -947,7 +947,7 @@ using @code{atexit} or @code{on_exit}.=0A= @c __libc_lock_lock @asulock @aculock=0A= @c calloc dup @ascuheap @acsmem=0A= @c __libc_lock_unlock @aculock=0A= -@c atomic_write_barrier dup ok=0A= +@c atomic_thread_fence_release dup ok=0A= The @code{atexit} function registers the function @var{function} to be=0A= called at normal program termination. The @var{function} is called with= =0A= no arguments.=0A= @@ -961,7 +961,7 @@ the function cannot be registered.=0A= @safety{@prelim{}@mtsafe{}@asunsafe{@ascuheap{} @asulock{}}@acunsafe{@acul= ock{} @acsmem{}}}=0A= @c on_exit @ascuheap @asulock @aculock @acsmem=0A= @c new_exitfn dup @ascuheap @asulock @aculock @acsmem=0A= -@c atomic_write_barrier dup ok=0A= +@c atomic_thread_fence_release dup ok=0A= This function is a somewhat more powerful variant of @code{atexit}. It=0A= accepts two arguments, a function @var{function} and an arbitrary=0A= pointer @var{arg}. At normal program termination, the @var{function} is= =0A= diff --git a/nptl/nptl-stack.c b/nptl/nptl-stack.c=0A= index 20ce78eddbf100833d453d7032f63bc2ba8f01c7..7c04e7faaae5c15bf5ad98c3293= 5bcba4849c1c1 100644=0A= --- a/nptl/nptl-stack.c=0A= +++ b/nptl/nptl-stack.c=0A= @@ -27,11 +27,11 @@ __nptl_stack_list_del (list_t *elem)=0A= {=0A= GL (dl_in_flight_stack) =3D (uintptr_t) elem;=0A= =0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= =0A= list_del (elem);=0A= =0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= =0A= GL (dl_in_flight_stack) =3D 0;=0A= }=0A= @@ -42,11 +42,11 @@ __nptl_stack_list_add (list_t *elem, list_t *list)=0A= {=0A= GL (dl_in_flight_stack) =3D (uintptr_t) elem | 1;=0A= =0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= =0A= list_add (elem, list);=0A= =0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= =0A= GL (dl_in_flight_stack) =3D 0;=0A= }=0A= diff --git a/nptl/pthread_mutex_setprioceiling.c b/nptl/pthread_mutex_setpr= ioceiling.c=0A= index 2d71a750c8981e8ca271c265031887e2c510583a..b574a77250664bbb1487c932b9a= 32a9dee415072 100644=0A= --- a/nptl/pthread_mutex_setprioceiling.c=0A= +++ b/nptl/pthread_mutex_setprioceiling.c=0A= @@ -113,7 +113,7 @@ __pthread_mutex_setprioceiling (pthread_mutex_t *mutex,= int prioceiling,=0A= newlock =3D (mutex->__data.__lock & ~PTHREAD_MUTEX_PRIO_CEILING_MASK);= =0A= mutex->__data.__lock =3D newlock=0A= | (prioceiling << PTHREAD_MUTEX_PRIO_CEILING_SHIFT);=0A= - atomic_full_barrier ();=0A= + atomic_thread_fence_seq_cst ();=0A= =0A= futex_wake ((unsigned int *)&mutex->__data.__lock, INT_MAX,=0A= PTHREAD_MUTEX_PSHARED (mutex));=0A= diff --git a/nptl/sem_post.c b/nptl/sem_post.c=0A= index 7ec21e92eb4c71d7f17764e96bc7603837f7522d..d4e37cb0888cb1004881e608b82= 147900bc420a5 100644=0A= --- a/nptl/sem_post.c=0A= +++ b/nptl/sem_post.c=0A= @@ -90,7 +90,7 @@ __old_sem_post (sem_t *sem)=0A= =0A= /* We must need to synchronize with consumers of this token, so the atom= ic=0A= increment must have release MO semantics. */=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= atomic_fetch_add_release (futex, 1);=0A= /* We always have to assume it is a shared semaphore. */=0A= futex_wake (futex, 1, LLL_SHARED);=0A= diff --git a/stdlib/msort.c b/stdlib/msort.c=0A= index cbe9a4a8fdb38113a4c18976c9f297be103d458f..e2f1eca94ad7e9005145c376b0d= e3dbd1ca14f18 100644=0A= --- a/stdlib/msort.c=0A= +++ b/stdlib/msort.c=0A= @@ -197,7 +197,7 @@ __qsort_r (void *b, size_t n, size_t s, __compar_d_fn_t= cmp, void *arg)=0A= phys_pages /=3D 4;=0A= =0A= /* Make sure phys_pages is written to memory. */=0A= - atomic_write_barrier ();=0A= + atomic_thread_fence_release ();=0A= =0A= pagesize =3D __sysconf (_SC_PAGESIZE);=0A= }=0A= diff --git a/sysdeps/aarch64/nptl/tls.h b/sysdeps/aarch64/nptl/tls.h=0A= index 08aa2eff891b7be32243e9955d998892807c7b2e..0e5b4ece6a118b4b066bd2fd024= dc85e978cc786 100644=0A= --- a/sysdeps/aarch64/nptl/tls.h=0A= +++ b/sysdeps/aarch64/nptl/tls.h=0A= @@ -108,7 +108,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/alpha/atomic-machine.h b/sysdeps/alpha/atomic-machine.= h=0A= index f384a2bf0b3376cf240dc25d501e1d64a94bffe1..7fbe5b87eebf323d38fe1349b02= aa56fe199cab3 100644=0A= --- a/sysdeps/alpha/atomic-machine.h=0A= +++ b/sysdeps/alpha/atomic-machine.h=0A= @@ -21,7 +21,3 @@=0A= =0A= /* XXX Is this actually correct? */=0A= #define ATOMIC_EXCHANGE_USES_CAS 1=0A= -=0A= -#define atomic_full_barrier() __asm ("mb" : : : "memory");=0A= -#define atomic_read_barrier() __asm ("mb" : : : "memory");=0A= -#define atomic_write_barrier() __asm ("wmb" : : : "memory");=0A= diff --git a/sysdeps/alpha/nptl/tls.h b/sysdeps/alpha/nptl/tls.h=0A= index 8f5b69ad3b1b0c557fa1bae55278547572a374cc..914dba422c50e4531d22eb459b4= 1c8b958a75263 100644=0A= --- a/sysdeps/alpha/nptl/tls.h=0A= +++ b/sysdeps/alpha/nptl/tls.h=0A= @@ -105,7 +105,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/arc/nptl/tls.h b/sysdeps/arc/nptl/tls.h=0A= index 7fc6602b236fa2455f8de4a0540442ae85d27c98..b2749f81d2980502043f507bf7c= 81da48f17aa9f 100644=0A= --- a/sysdeps/arc/nptl/tls.h=0A= +++ b/sysdeps/arc/nptl/tls.h=0A= @@ -113,7 +113,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/arm/nptl/tls.h b/sysdeps/arm/nptl/tls.h=0A= index 7657ca3dccc2d929c71236d42fc060a4b4902e2b..b1389ba034966aff17692f2b6d0= e7b04a0baf9a0 100644=0A= --- a/sysdeps/arm/nptl/tls.h=0A= +++ b/sysdeps/arm/nptl/tls.h=0A= @@ -99,7 +99,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/csky/nptl/tls.h b/sysdeps/csky/nptl/tls.h=0A= index 58d6ab0fb2ae90de50cffd5b4a98426c6a793050..ac54606c3c0e28c1c8d57a6475d= 9249ca3566abe 100644=0A= --- a/sysdeps/csky/nptl/tls.h=0A= +++ b/sysdeps/csky/nptl/tls.h=0A= @@ -128,7 +128,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/hppa/dl-fptr.c b/sysdeps/hppa/dl-fptr.c=0A= index 40bf5cd3b306315d8eeb6bdba2b2b46b1ea5059e..0562467d6f79f76b78b2cf169fd= d059a993296d3 100644=0A= --- a/sysdeps/hppa/dl-fptr.c=0A= +++ b/sysdeps/hppa/dl-fptr.c=0A= @@ -369,7 +369,7 @@ _dl_lookup_address (const void *address)=0A= =0A= /* First load the relocation offset. */=0A= reloc_arg =3D (ElfW(Word)) desc[1];=0A= - atomic_full_barrier();=0A= + atomic_thread_fence_seq_cst ();=0A= =0A= /* Then load first word of candidate descriptor. It should be a pointer= =0A= with word alignment and point to memory that can be read. */=0A= diff --git a/sysdeps/hppa/dl-machine.h b/sysdeps/hppa/dl-machine.h=0A= index c865713be1e3f8e0430bbb35c8db7ebe3e7a6abf..61635ca9115e1fa77305eaa3cc4= ab5bf9bb91d7b 100644=0A= --- a/sysdeps/hppa/dl-machine.h=0A= +++ b/sysdeps/hppa/dl-machine.h=0A= @@ -136,7 +136,7 @@ elf_machine_fixup_plt (struct link_map *map, lookup_t t= ,=0A= /* Need to ensure that the gp is visible before the code=0A= entry point is updated */=0A= rfdesc[1] =3D value.gp;=0A= - atomic_full_barrier();=0A= + atomic_thread_fence_seq_cst ();=0A= rfdesc[0] =3D value.ip;=0A= }=0A= else=0A= diff --git a/sysdeps/hppa/nptl/tls.h b/sysdeps/hppa/nptl/tls.h=0A= index e6b0bd5c7182b497aaf0d2bb08f62551a223c403..5b2495637b8aec9df3c8b3d47a2= b46aa632c84da 100644=0A= --- a/sysdeps/hppa/nptl/tls.h=0A= +++ b/sysdeps/hppa/nptl/tls.h=0A= @@ -133,7 +133,7 @@ static inline void __set_cr27(struct pthread *cr27)=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/htl/pt-once.c b/sysdeps/htl/pt-once.c=0A= index b85b196645958fc7f47b08b39e91077b82817cdc..55db6c3d7176a9ca6cf2d0caccc= 1cf01aeb5ea2f 100644=0A= --- a/sysdeps/htl/pt-once.c=0A= +++ b/sysdeps/htl/pt-once.c=0A= @@ -33,7 +33,7 @@ __pthread_once (pthread_once_t *once_control, void (*init= _routine) (void))=0A= {=0A= ASSERT_TYPE_SIZE (pthread_once_t, __SIZEOF_PTHREAD_ONCE_T);=0A= =0A= - atomic_full_barrier ();=0A= + atomic_thread_fence_seq_cst ();=0A= if (once_control->__run =3D=3D 0)=0A= {=0A= __pthread_spin_wait (&once_control->__lock);=0A= @@ -44,7 +44,7 @@ __pthread_once (pthread_once_t *once_control, void (*init= _routine) (void))=0A= init_routine ();=0A= pthread_cleanup_pop (0);=0A= =0A= - atomic_full_barrier ();=0A= + atomic_thread_fence_seq_cst ();=0A= once_control->__run =3D 1;=0A= }=0A= =0A= diff --git a/sysdeps/ia64/nptl/tls.h b/sysdeps/ia64/nptl/tls.h=0A= index d2411b3c1ac29733c0bb3683d83388e2e0e8e277..7709e644ee04ebc935dc6598064= 81eebcb4129f0 100644=0A= --- a/sysdeps/ia64/nptl/tls.h=0A= +++ b/sysdeps/ia64/nptl/tls.h=0A= @@ -157,7 +157,7 @@ register struct pthread *__thread_self __asm__("r13");= =0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/m68k/nptl/tls.h b/sysdeps/m68k/nptl/tls.h=0A= index 742e1b6767d99fa6011ac1d207264c7b82e53787..dfba7a568016b8e10dac6c21d65= c785eaab12a09 100644=0A= --- a/sysdeps/m68k/nptl/tls.h=0A= +++ b/sysdeps/m68k/nptl/tls.h=0A= @@ -132,7 +132,7 @@ extern void * __m68k_read_tp (void);=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \=0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/mach/hurd/htl/pt-mutex-destroy.c b/sysdeps/mach/hurd/h= tl/pt-mutex-destroy.c=0A= index 71f789cbdfa20b79f9e3cef5a2523d4e243b4f19..feb9085af9499b5d954a1bf4f04= d9cbcb804e8cf 100644=0A= --- a/sysdeps/mach/hurd/htl/pt-mutex-destroy.c=0A= +++ b/sysdeps/mach/hurd/htl/pt-mutex-destroy.c=0A= @@ -26,7 +26,7 @@=0A= int=0A= __pthread_mutex_destroy (pthread_mutex_t *mtxp)=0A= {=0A= - atomic_read_barrier ();=0A= + atomic_thread_fence_acquire ();=0A= if (*(volatile unsigned int *) &mtxp->__lock !=3D 0)=0A= return EBUSY;=0A= =0A= diff --git a/sysdeps/mach/hurd/htl/pt-mutex.h b/sysdeps/mach/hurd/htl/pt-mu= tex.h=0A= index 4021e72a6e8d15316336296ff732a4e7fd1acdff..ebdf8a5fbde0f755c7625cd38ad= 185ee0c977b5f 100644=0A= --- a/sysdeps/mach/hurd/htl/pt-mutex.h=0A= +++ b/sysdeps/mach/hurd/htl/pt-mutex.h=0A= @@ -54,7 +54,7 @@=0A= if (ret =3D=3D EOWNERDEAD) \=0A= { \=0A= mtxp->__lock =3D mtxp->__lock | LLL_DEAD_OWNER; \=0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= } \=0A= } \=0A= diff --git a/sysdeps/microblaze/nptl/tls.h b/sysdeps/microblaze/nptl/tls.h= =0A= index 588fd1c5d63ee4e6a1b284cc19e216b6730a2091..30e5d628be8b78cf9c7b8e9386a= b1b2355819f4a 100644=0A= --- a/sysdeps/microblaze/nptl/tls.h=0A= +++ b/sysdeps/microblaze/nptl/tls.h=0A= @@ -110,7 +110,7 @@ typedef struct=0A= do = \=0A= { = \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; = \=0A= - atomic_write_barrier (); = \=0A= + atomic_thread_fence_release (); = \=0A= } = \=0A= while (0)=0A= =0A= diff --git a/sysdeps/mips/nptl/tls.h b/sysdeps/mips/nptl/tls.h=0A= index 2aa7cb4bb8d0b5a31889aa33d5751104ff1e4f45..e4c5d2a876db7943b38daa270f4= 681d17b441c58 100644=0A= --- a/sysdeps/mips/nptl/tls.h=0A= +++ b/sysdeps/mips/nptl/tls.h=0A= @@ -160,7 +160,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/nios2/nptl/tls.h b/sysdeps/nios2/nptl/tls.h=0A= index cb231e2a4bbfa52495c4c017a7d3e1c6dd7937ca..50dbbef119af30112136a9bef18= 7c79037d0849d 100644=0A= --- a/sysdeps/nios2/nptl/tls.h=0A= +++ b/sysdeps/nios2/nptl/tls.h=0A= @@ -140,7 +140,7 @@ register struct pthread *__thread_self __asm__("r23");= =0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/or1k/nptl/tls.h b/sysdeps/or1k/nptl/tls.h=0A= index e82f444738de222c0e4866d5a2ab8191ce99ddc9..886c017be12d06ee63198a36917= c59e24be77a60 100644=0A= --- a/sysdeps/or1k/nptl/tls.h=0A= +++ b/sysdeps/or1k/nptl/tls.h=0A= @@ -175,7 +175,7 @@ register tcbhead_t *__thread_self __asm__("r10");=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \=0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/powerpc/nptl/tls.h b/sysdeps/powerpc/nptl/tls.h=0A= index e62a96238aa95c79ac1f749b4dbf03985b6e15d4..c8d233a7347f609b4cdbffb5daf= a2f55e18ac18e 100644=0A= --- a/sysdeps/powerpc/nptl/tls.h=0A= +++ b/sysdeps/powerpc/nptl/tls.h=0A= @@ -224,7 +224,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/p= owerpc32/atomic-machine.h=0A= index f72d4be13709e38006255d236efb0e94f3976e68..6a2aae8bdb34281144e68109243= 77a6a62857d15 100644=0A= --- a/sysdeps/powerpc/powerpc32/atomic-machine.h=0A= +++ b/sysdeps/powerpc/powerpc32/atomic-machine.h=0A= @@ -36,24 +36,3 @@=0A= =0A= #define __HAVE_64B_ATOMICS 0=0A= #define ATOMIC_EXCHANGE_USES_CAS 1=0A= -=0A= -#ifdef _ARCH_PWR4=0A= -/*=0A= - * Newer powerpc64 processors support the new "light weight" sync (lwsync)= =0A= - * So if the build is using -mcpu=3D[power4,power5,power5+,970] we can=0A= - * safely use lwsync.=0A= - */=0A= -# define atomic_read_barrier() __asm ("lwsync" ::: "memory")=0A= -/*=0A= - * "light weight" sync can also be used for the release barrier.=0A= - */=0A= -# define atomic_write_barrier() __asm ("lwsync" ::: "memory")=0A= -#else=0A= -/*=0A= - * Older powerpc32 processors don't support the new "light weight"=0A= - * sync (lwsync). So the only safe option is to use normal sync=0A= - * for all powerpc32 applications.=0A= - */=0A= -# define atomic_read_barrier() __asm ("sync" ::: "memory")=0A= -# define atomic_write_barrier() __asm ("sync" ::: "memory")=0A= -#endif=0A= diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/p= owerpc64/atomic-machine.h=0A= index fcb1592be9ad6a3981f56c513deac2f5f8ac5bb7..2932f889c5bc6d0fa49d5ad3687= 5b50c27ad07e9 100644=0A= --- a/sysdeps/powerpc/powerpc64/atomic-machine.h=0A= +++ b/sysdeps/powerpc/powerpc64/atomic-machine.h=0A= @@ -36,12 +36,3 @@=0A= =0A= #define __HAVE_64B_ATOMICS 1=0A= #define ATOMIC_EXCHANGE_USES_CAS 1=0A= -=0A= -/*=0A= - * All powerpc64 processors support the new "light weight" sync (lwsync).= =0A= - */=0A= -#define atomic_read_barrier() __asm ("lwsync" ::: "memory")=0A= -/*=0A= - * "light weight" sync can also be used for the release barrier.=0A= - */=0A= -#define atomic_write_barrier() __asm ("lwsync" ::: "memory")=0A= diff --git a/sysdeps/riscv/nptl/tls.h b/sysdeps/riscv/nptl/tls.h=0A= index 700c2f51899b0385d7ebaa4810c84de4fa6f2b45..020a986ceee89e1feb8f76c51f2= 24a8faea71bbb 100644=0A= --- a/sysdeps/riscv/nptl/tls.h=0A= +++ b/sysdeps/riscv/nptl/tls.h=0A= @@ -123,7 +123,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/s390/nptl/tls.h b/sysdeps/s390/nptl/tls.h=0A= index 98d7870148ce6bc1d6397b1465dfabe96f7280b2..f1664d9ade6fd562db38c3dddd3= fa6237a47faea 100644=0A= --- a/sysdeps/s390/nptl/tls.h=0A= +++ b/sysdeps/s390/nptl/tls.h=0A= @@ -167,7 +167,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/sh/nptl/tls.h b/sysdeps/sh/nptl/tls.h=0A= index 1530489a6ce4286bc5146e6cd83e3b463b965467..00ae1b998b9e0b1e6c347c4be4e= 99a90e530e924 100644=0A= --- a/sysdeps/sh/nptl/tls.h=0A= +++ b/sysdeps/sh/nptl/tls.h=0A= @@ -139,7 +139,7 @@ typedef struct=0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/sparc/atomic-machine.h b/sysdeps/sparc/atomic-machine.= h=0A= index a7042f1ee546b9f238153cb923409d42eb45cc03..1f0eb0a9b1171c06dc19dc21c4f= e7de94adc4bce 100644=0A= --- a/sysdeps/sparc/atomic-machine.h=0A= +++ b/sysdeps/sparc/atomic-machine.h=0A= @@ -29,13 +29,6 @@=0A= #define ATOMIC_EXCHANGE_USES_CAS __HAVE_64B_ATOMICS=0A= =0A= #ifdef __sparc_v9__=0A= -# define atomic_full_barrier() \=0A= - __asm __volatile ("membar #LoadLoad | #LoadStore" \=0A= - " | #StoreLoad | #StoreStore" : : : "memory")=0A= -# define atomic_read_barrier() \=0A= - __asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory")=0A= -# define atomic_write_barrier() \=0A= - __asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory")=0A= =0A= extern void __cpu_relax (void);=0A= # define atomic_spin_nop() __cpu_relax ()=0A= diff --git a/sysdeps/sparc/nptl/tls.h b/sysdeps/sparc/nptl/tls.h=0A= index 95a69cb8249dc79c3a063637a21d976d2660c48f..bc7ada0d3fe66751506e1cf5516= f14ec2c205af8 100644=0A= --- a/sysdeps/sparc/nptl/tls.h=0A= +++ b/sysdeps/sparc/nptl/tls.h=0A= @@ -140,7 +140,7 @@ register struct pthread *__thread_self __asm__("%g7");= =0A= do \=0A= { \=0A= THREAD_SELF->header.gscope_flag =3D THREAD_GSCOPE_FLAG_USED; \= =0A= - atomic_write_barrier (); \=0A= + atomic_thread_fence_release (); \=0A= } \=0A= while (0)=0A= =0A= diff --git a/sysdeps/unix/sysv/linux/arm/atomic-machine.h b/sysdeps/unix/sy= sv/linux/arm/atomic-machine.h=0A= deleted file mode 100644=0A= index 20068c72f359442769f8d49e11f7e771c922ef0b..000000000000000000000000000= 0000000000000=0A= --- a/sysdeps/unix/sysv/linux/arm/atomic-machine.h=0A= +++ /dev/null=0A= @@ -1,115 +0,0 @@=0A= -/* Atomic operations. ARM/Linux version.=0A= - Copyright (C) 2002-2022 Free Software Foundation, Inc.=0A= - This file is part of the GNU C Library.=0A= -=0A= - The GNU C Library is free software; you can redistribute it and/or=0A= - modify it under the terms of the GNU Lesser General Public=0A= - License as published by the Free Software Foundation; either=0A= - version 2.1 of the License, or (at your option) any later version.=0A= -=0A= - The GNU C Library is distributed in the hope that it will be useful,=0A= - but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU=0A= - Lesser General Public License for more details.=0A= -=0A= - You should have received a copy of the GNU Lesser General Public=0A= - License along with the GNU C Library. If not, see=0A= - . */=0A= -=0A= -#include =0A= -=0A= -/* If the compiler doesn't provide a primitive, we'll use this macro=0A= - to get assistance from the kernel. */=0A= -#ifdef __thumb2__=0A= -# define __arm_assisted_full_barrier() \=0A= - __asm__ __volatile__ \=0A= - ("movw\tip, #0x0fa0\n\t" \=0A= - "movt\tip, #0xffff\n\t" \=0A= - "blx\tip" \=0A= - : : : "ip", "lr", "cc", "memory");=0A= -#else=0A= -# define __arm_assisted_full_barrier() \=0A= - __asm__ __volatile__ \=0A= - ("mov\tip, #0xffff0fff\n\t" \=0A= - "mov\tlr, pc\n\t" \=0A= - "add\tpc, ip, #(0xffff0fa0 - 0xffff0fff)" \=0A= - : : : "ip", "lr", "cc", "memory");=0A= -#endif=0A= -=0A= -/* Atomic compare and exchange. This sequence relies on the kernel to=0A= - provide a compare and exchange operation which is atomic on the=0A= - current architecture, either via cleverness on pre-ARMv6 or via=0A= - ldrex / strex on ARMv6.=0A= -=0A= - It doesn't matter what register is used for a_oldval2, but we must=0A= - specify one to work around GCC PR rtl-optimization/21223. Otherwise=0A= - it may cause a_oldval or a_tmp to be moved to a different register.=0A= -=0A= - We use the union trick rather than simply using __typeof (...) in the= =0A= - declarations of A_OLDVAL et al because when NEWVAL or OLDVAL is of the= =0A= - form *PTR and PTR has a 'volatile ... *' type, then __typeof (*PTR) has= =0A= - a 'volatile ...' type and this triggers -Wvolatile-register-var to=0A= - complain about 'register volatile ... asm ("reg")'.=0A= -=0A= - We use the same union trick in the declaration of A_PTR because when=0A= - MEM is of the from *PTR and PTR has a 'const ... *' type, then __typeof= =0A= - (*PTR) has a 'const ...' type and this enables the compiler to substitu= te=0A= - the variable with its initializer in asm statements, which may cause th= e=0A= - corresponding operand to appear in a different register. */=0A= -#ifdef __thumb2__=0A= -/* Thumb-2 has ldrex/strex. However it does not have barrier instructions= ,=0A= - so we still need to use the kernel helper. */=0A= -# define __arm_assisted_compare_and_exchange_val_32_acq(mem, newval, oldva= l) \=0A= - ({ union { __typeof (mem) a; uint32_t v; } mem_arg =3D { .a =3D (mem) };= \=0A= - union { __typeof (oldval) a; uint32_t v; } oldval_arg =3D { .a =3D (o= ldval) };\=0A= - union { __typeof (newval) a; uint32_t v; } newval_arg =3D { .a =3D (n= ewval) };\=0A= - register uint32_t a_oldval asm ("r0"); \=0A= - register uint32_t a_newval asm ("r1") =3D newval_arg.v; \=0A= - register uint32_t a_ptr asm ("r2") =3D mem_arg.v; \=0A= - register uint32_t a_tmp asm ("r3"); \=0A= - register uint32_t a_oldval2 asm ("r4") =3D oldval_arg.v; \=0A= - __asm__ __volatile__ \=0A= - ("0:\tldr\t%[tmp],[%[ptr]]\n\t" \=0A= - "cmp\t%[tmp], %[old2]\n\t" \=0A= - "bne\t1f\n\t" \=0A= - "mov\t%[old], %[old2]\n\t" \=0A= - "movw\t%[tmp], #0x0fc0\n\t" \=0A= - "movt\t%[tmp], #0xffff\n\t" \=0A= - "blx\t%[tmp]\n\t" \=0A= - "bcc\t0b\n\t" \=0A= - "mov\t%[tmp], %[old2]\n\t" \=0A= - "1:" \=0A= - : [old] "=3D&r" (a_oldval), [tmp] "=3D&r" (a_tmp) \=0A= - : [new] "r" (a_newval), [ptr] "r" (a_ptr), \=0A= - [old2] "r" (a_oldval2) \=0A= - : "ip", "lr", "cc", "memory"); \=0A= - (__typeof (oldval)) a_tmp; })=0A= -#else=0A= -# define __arm_assisted_compare_and_exchange_val_32_acq(mem, newval, oldva= l) \=0A= - ({ union { __typeof (mem) a; uint32_t v; } mem_arg =3D { .a =3D (mem) };= \=0A= - union { __typeof (oldval) a; uint32_t v; } oldval_arg =3D { .a =3D (o= ldval) };\=0A= - union { __typeof (newval) a; uint32_t v; } newval_arg =3D { .a =3D (n= ewval) };\=0A= - register uint32_t a_oldval asm ("r0"); \=0A= - register uint32_t a_newval asm ("r1") =3D newval_arg.v; \=0A= - register uint32_t a_ptr asm ("r2") =3D mem_arg.v; \=0A= - register uint32_t a_tmp asm ("r3"); \=0A= - register uint32_t a_oldval2 asm ("r4") =3D oldval_arg.v; \=0A= - __asm__ __volatile__ \=0A= - ("0:\tldr\t%[tmp],[%[ptr]]\n\t" \=0A= - "cmp\t%[tmp], %[old2]\n\t" \=0A= - "bne\t1f\n\t" \=0A= - "mov\t%[old], %[old2]\n\t" \=0A= - "mov\t%[tmp], #0xffff0fff\n\t" \=0A= - "mov\tlr, pc\n\t" \=0A= - "add\tpc, %[tmp], #(0xffff0fc0 - 0xffff0fff)\n\t" \=0A= - "bcc\t0b\n\t" \=0A= - "mov\t%[tmp], %[old2]\n\t" \=0A= - "1:" \=0A= - : [old] "=3D&r" (a_oldval), [tmp] "=3D&r" (a_tmp) \=0A= - : [new] "r" (a_newval), [ptr] "r" (a_ptr), \=0A= - [old2] "r" (a_oldval2) \=0A= - : "ip", "lr", "cc", "memory"); \=0A= - (__typeof (oldval)) a_tmp; })=0A= -#endif=0A= -=0A= -#include =0A= diff --git a/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h b/sysde= ps/unix/sysv/linux/m68k/coldfire/atomic-machine.h=0A= index 6f83fb2965bd162f0f76e0e3586472ade39af607..02e54847a42bfbc93ae1e07b7e3= 2965be644daba 100644=0A= --- a/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h=0A= +++ b/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h=0A= @@ -25,7 +25,4 @@=0A= /* XXX Is this actually correct? */=0A= #define ATOMIC_EXCHANGE_USES_CAS 1=0A= =0A= -# define atomic_full_barrier() \=0A= - (INTERNAL_SYSCALL_CALL (atomic_barrier), (void) 0)=0A= -=0A= #endif=0A= diff --git a/sysdeps/x86/atomic-machine.h b/sysdeps/x86/atomic-machine.h=0A= index b9be51c52d8cbef2a95a62192c8ef7011e7f2c12..98541a2d06ff5e4aa8c789ab740= 5215097471971 100644=0A= --- a/sysdeps/x86/atomic-machine.h=0A= +++ b/sysdeps/x86/atomic-machine.h=0A= @@ -32,9 +32,6 @@=0A= #endif=0A= #define ATOMIC_EXCHANGE_USES_CAS 0=0A= =0A= -#define atomic_read_barrier() __asm ("" ::: "memory")=0A= -#define atomic_write_barrier() __asm ("" ::: "memory")=0A= -=0A= #define atomic_spin_nop() __asm ("pause")=0A= =0A= #endif /* atomic-machine.h */=0A=