From: Tejas Belagod <Tejas.Belagod@arm.com>
To: Szabolcs Nagy <Szabolcs.Nagy@arm.com>,
"libc-alpha@sourceware.org" <libc-alpha@sourceware.org>
Subject: RE: [PATCH] AArch64: Add asymmetric faulting mode for tag violations in mem.tagging tunable
Date: Fri, 1 Jul 2022 06:41:11 +0000 [thread overview]
Message-ID: <AS8PR08MB707956BA8A730478C2FF3E8AEABD9@AS8PR08MB7079.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <Yr2fNYzC5FQS4LWV@arm.com>
> -----Original Message-----
> From: Szabolcs Nagy <Szabolcs.Nagy@arm.com>
> Sent: Thursday, June 30, 2022 6:34 PM
> To: Tejas Belagod <Tejas.Belagod@arm.com>; libc-alpha@sourceware.org
> Subject: Re: [PATCH] AArch64: Add asymmetric faulting mode for tag
> violations in mem.tagging tunable
>
> The 06/30/2022 12:07, Szabolcs Nagy via Libc-alpha wrote:
> > The 06/27/2022 18:00, Tejas Belagod wrote:
> > > Hi,
> > >
> > > The new asymmetric mode is available when HWCAP2_MTE3 is set
> > > (support is available), bit2 is set in the tunable (user request per
> > > application), and the system is configured such that the asymmetric
> > > mode is preferred over sync or async (per-cpu system-wide setting).
> > >
> > > OK for master?
> > >
> > > Thanks,
> > > Tejas.
> >
> > This is ok.
> >
> > Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
>
> committed for you.
Thanks you.
prev parent reply other threads:[~2022-07-01 6:41 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 18:00 Tejas Belagod
2022-06-30 11:07 ` Szabolcs Nagy
2022-06-30 13:03 ` Szabolcs Nagy
2022-07-01 6:41 ` Tejas Belagod [this message]
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