From: Tejas Belagod <Tejas.Belagod@arm.com>
To: "libc-alpha@sourceware.org" <libc-alpha@sourceware.org>
Cc: Szabolcs Nagy <Szabolcs.Nagy@arm.com>
Subject: Reset HWCAP2_AFP bits in FPCR for default fenv.
Date: Wed, 29 Jun 2022 09:34:33 +0000 [thread overview]
Message-ID: <AS8PR08MB7079624B79439292B360CCAAEABB9@AS8PR08MB7079.eurprd08.prod.outlook.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 475 bytes --]
Hi,
The AFP feature (Alternate floating-point behavior) was added in Armv8.7-A and
introduced new FPCR bits.
Currently, HWCAP2_AFP bits (bit 0, 1, 2) in FPCR are preserved when fenv is
set to default environment. This is a deviation from standard behavior.
Clear these bits when setting the fenv to default.
There is no libc API to modify the new FPCR bits. Restoring those bits matters
if the user changed them directly.
OK for master?
Thanks,
Tejas.
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diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb6a90a4d6ac9af1f8874fd71c379e62..429f4910e7a165a7ba8170b173c4fbb3960afa3f 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -46,7 +46,7 @@
contents. These two masks indicate which bits in each of FPCR and
FPSR should not be changed. */
-#define _FPU_RESERVED 0xfe0fe0ff
+#define _FPU_RESERVED 0xfe0fe0f8
#define _FPU_FPSR_RESERVED 0x0fffffe0
#define _FPU_DEFAULT 0x00000000
next reply other threads:[~2022-06-29 9:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-29 9:34 Tejas Belagod [this message]
2022-06-29 9:54 ` Florian Weimer
2022-06-29 11:24 ` Szabolcs Nagy
2022-06-29 16:53 ` Joseph Myers
2022-06-30 10:19 ` Tejas Belagod
2022-06-30 10:42 ` Florian Weimer
2022-06-30 10:56 ` Tejas Belagod
2022-07-01 6:40 Tejas Belagod
2022-07-04 13:51 ` Szabolcs Nagy
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