[PATCH] AArch64: Add asymmetric faulting mode for tag violations in mem.tagging tunable

[Tejas Belagod <Tejas.Belagod@arm.com>]

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Hi,

The new asymmetric mode is available when HWCAP2_MTE3 is set (support is
available), bit2 is set in the tunable (user request per application),
and the system is configured such that the asymmetric mode is preferred over
sync or async (per-cpu system-wide setting).

OK for master?

Thanks,
Tejas.

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diff --git a/manual/tunables.texi b/manual/tunables.texi
index 1482412078d21cc8da22a62ff4acac3e5297eff9..1d6befaf4a40865a4eee6a6a7a34fa39258f764b 100644
--- a/manual/tunables.texi
+++ b/manual/tunables.texi
@@ -602,6 +602,9 @@ Bit 1 enables precise faulting mode for tag violations on systems that
 support deferred tag violation reporting.  This may cause programs
 to run more slowly.
 
+Bit 2 enables either precise or deferred faulting mode for tag violations
+whichever is preferred by the system.
+
 Other bits are currently reserved.
 
 @Theglibc{} startup code will automatically enable memory tagging
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d00327e56b6c85a07eb68435de1dda5dae..d14c0f4e1f2905148ac55a4569fd3e12f9a1d7fe 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -108,7 +108,13 @@ init_cpu_features (struct cpu_features *cpu_features)
   TUNABLE_SET (glibc, mem, tagging, cpu_features->mte_state);
 # endif
 
-  if (cpu_features->mte_state & 2)
+  if (cpu_features->mte_state & 4)
+    /* Enable choosing system-preferred faulting mode.  */
+    __prctl (PR_SET_TAGGED_ADDR_CTRL,
+	     (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC
+	      | MTE_ALLOWED_TAGS),
+	     0, 0, 0);
+  else if (cpu_features->mte_state & 2)
     __prctl (PR_SET_TAGGED_ADDR_CTRL,
 	     (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | MTE_ALLOWED_TAGS),
 	     0, 0, 0);