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From: John David Anglin <dave.anglin@bell.net>
To: Mike Frysinger <vapier@gentoo.org>
Cc: libc-alpha@sourceware.org, carlos@systemhalted.org
Subject: Re: [PATCH] hppa: fix __O_SYNC to match the kernel
Date: Sun, 01 Mar 2015 19:55:00 -0000	[thread overview]
Message-ID: <BLU436-SMTP175B7131A983C54990446FB97130@phx.gbl> (raw)
In-Reply-To: <20150227065339.GO29461@vapier>

Hi Mike,

On 2015-02-27, at 1:53 AM, Mike Frysinger wrote:

> On 24 Feb 2015 09:48, John David Anglin wrote:
>> Mike, thanks for sending this change.  Reminds me I should go through 
>> the Debian glibc
>> patches and see what else needs sending.
> 
> this should be an easy one:
> https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=1c1d3f4f11b4a911a3b6ffab0aac61d5f8e02873

I started to write a ChangeLog entry and realized that there is a problem with the change
to feholdexcept.c.  I believe the second set of bufptr needs to be removed.

> 
> if you could provide context, i could shepherd it through.

The patch is intended to fix problems in accessing and updating the floating-point status register
and exception registers.

Originally, the routines were written to save and restore the status register and the entire set of 
(all seven) exception registers.  At some point, the code was changed to just manipulate the status
register and the first exception register.  A couple of bugs were introduced when this was done.

In fesetenv.c, the post increment of bufptr was retained in the first asm but the constraint for it
does not indicate that bufptr is modified.  As a result, GCC miscompiled fesetenv.  We get better
code by not modifying bufptr as GCC doesn't have to reload bufptr.

The main bug in feholdexcept is the second set of bufptr.  This existed to the restore the exception
registers in reverse order.  This statement should have been removed when the code was changed
to only update the status and first exception registers.  The offset used in the statement is also off
by a factor two, so it probably never worked correctly.  With the current patch, the code loads zero to
the status and exception register.  As a result, the T bit is not set properly.

I will test a revised change to feholdexcept and get back to you.

Dave
--
John David Anglin	dave.anglin@bell.net



  reply	other threads:[~2015-03-01 19:55 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-24  5:19 Mike Frysinger
2015-02-24 14:50 ` John David Anglin
2015-02-24 16:20   ` Joseph Myers
2015-02-27  5:06     ` Carlos O'Donell
2015-02-27  6:53   ` Mike Frysinger
2015-03-01 19:55     ` John David Anglin [this message]
2015-03-01 22:24       ` Joseph Myers
2015-03-02 13:18         ` John David Anglin
2015-03-02 14:09           ` Joseph Myers
2015-03-11  7:33           ` Mike Frysinger
2015-03-08 19:52       ` Carlos O'Donell
2015-03-08 21:30         ` John David Anglin
2015-03-09 12:36           ` Carlos O'Donell
2015-03-07 17:13     ` John David Anglin
2015-03-08 19:53       ` Carlos O'Donell
2015-03-11  6:29       ` Carlos O'Donell
2015-02-27  6:46 ` Mike Frysinger

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