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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id s197-20020a37a9ce000000b006eed75805a2sm954055qke.126.2022.12.22.13.39.08 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Dec 2022 13:39:08 -0800 (PST) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-3b48b139b46so42825417b3.12 for ; Thu, 22 Dec 2022 13:39:08 -0800 (PST) X-Received: by 2002:a0d:d883:0:b0:3d7:28d5:1c6f with SMTP id a125-20020a0dd883000000b003d728d51c6fmr516201ywe.227.1671745148129; Thu, 22 Dec 2022 13:39:08 -0800 (PST) MIME-Version: 1.0 References: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> <1631497278-29829-3-git-send-email-vincent.chen@sifive.com> <871r5sd1zq.fsf@oldenburg.str.redhat.com> <20210913135247.GL13220@brightrain.aerifal.cx> <87sfy5ndid.fsf@oldenburg.str.redhat.com> <73c0124c-4794-6e40-460c-b26df407f322@rivosinc.com> <50c598a6-e3b3-3062-abe7-23a406067533@rivosinc.com> <7430f494-9b43-5e03-c1e9-6b83e2611a11@rivosinc.com> <6b79d32c-2e59-09b6-2132-4b99e2a8923e@rivosinc.com> In-Reply-To: <6b79d32c-2e59-09b6-2132-4b99e2a8923e@rivosinc.com> From: Andrew Waterman Date: Thu, 22 Dec 2022 13:38:59 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break To: Vineet Gupta Cc: Richard Henderson , Vincent Chen , Florian Weimer , Rich Felker , Palmer Dabbelt , Kito Cheng , =?UTF-8?Q?Christoph_M=C3=BCllner?= , davidlt@rivosinc.com, Arnd Bergmann , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Philipp Tomsich , Szabolcs Nagy , Andy Chiu , Greentime Hu , Aaron Durbin , Andrew de los Reyes , linux-riscv , GNU C Library Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Dec 22, 2022 at 12:30 PM Vineet Gupta wrote: > > > > On 12/21/22 21:32, Richard Henderson wrote: > > On 12/21/22 11:52, Vineet Gupta wrote: > >> This is not an issue, if we don't change sigcontext (in kernel and > >> glibc) - it is essentially the case of existing binaries. kernel > >> still saves regs on user stack, in > >> rt_sigframe, its just that userspace is not able to access them in > >> SA_SIGINFO signal > >> handers. aarch64 have this implemented this approach and it is likely > >> they can't do > >> that either for SVE regs. > > > > aarch64 can certainly access the SVE regs on the signal stack. It > > simply requires that you parse the chain of extensions within > > __reserved to find it. > > It's quite well designed, really. > > Yep I've been staring at it this week and really appreciate the > extensible design. Indeed one can do thru the existing __reserved in > sigcontext to access that from userspace. Sorry y'all had to reverse-engineer our logic: this was exactly our intent for those reserved words when we defined the current ABI. It's also why the current ABI requires them to be zero: as a sentinel to signify the end of the list of extension areas. > > > > > > What you can't do is "only" declare a sigcontext_t and be able to > > construct a new context, nor copy the entire context via structure > > assignment. > > > > There is room within the risc-v context for a similar scheme, via > > > > sigcontext.sc_fpregs.q.reserved[3] > > > > E.g. > > > > reserved[0] -> magic > > reserved[1] -> displacement to "extension area" > > reserved[2] -> size of "extension area" > > > > Thus the area can be located anywhere within 4GB and expand to 4GB. > > Not that I'd hope any signal frame would require 4GB. :-) > > Looks like we almost missed this. Thx for the pointer Richard. > > -Vineet >