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[209.85.166.169]) by smtp.gmail.com with ESMTPSA id v8-20020a92cd48000000b0030ed915bceasm3705400ilq.73.2023.02.06.16.23.16 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Feb 2023 16:23:17 -0800 (PST) Received: by mail-il1-f169.google.com with SMTP id s10so1064597iln.6 for ; Mon, 06 Feb 2023 16:23:16 -0800 (PST) X-Received: by 2002:a92:6a08:0:b0:30f:641b:d126 with SMTP id f8-20020a926a08000000b0030f641bd126mr517140ilc.71.1675729396608; Mon, 06 Feb 2023 16:23:16 -0800 (PST) MIME-Version: 1.0 References: <20230207001618.458947-1-christoph.muellner@vrull.eu> <20230207001618.458947-20-christoph.muellner@vrull.eu> In-Reply-To: <20230207001618.458947-20-christoph.muellner@vrull.eu> From: Andrew Waterman Date: Mon, 6 Feb 2023 16:23:05 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 19/19] riscv: Add __riscv_cpu_relax() to allow yielding in busy loops To: Christoph Muellner Cc: libc-alpha@sourceware.org, Palmer Dabbelt , Darius Rad , DJ Delorie , Vineet Gupta , Kito Cheng , Jeff Law , Philipp Tomsich , Heiko Stuebner Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Note that all implementations must support `pause`, since it's a HINT instruction encoded within a base-ISA instruction that has no architecturally visible effect. So it's not clear to me that there's any virtue in distinguishing implementations that claim to support Zihintpause from those that don't. On Mon, Feb 6, 2023 at 4:17 PM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > The spinning loop of PTHREAD_MUTEX_ADAPTIVE_NP provides the hook > atomic_spin_nop() that can be used by architectures. > > On RISC-V we have two instructions that can be used here: > * WRS.STO from the Zawrs extension > * PAUSE from the Zihintpause extension > > Let's use these instructions and prefer WRS.STO over PAUSE > (based on availability of the corresponding ISA extension > at runtime). > > Signed-off-by: Christoph M=C3=BCllner > --- > sysdeps/riscv/multiarch/Makefile | 5 +++ > sysdeps/riscv/multiarch/cpu_relax.c | 36 +++++++++++++++++ > sysdeps/riscv/multiarch/cpu_relax_impl.S | 40 +++++++++++++++++++ > .../unix/sysv/linux/riscv/atomic-machine.h | 3 ++ > 4 files changed, 84 insertions(+) > create mode 100644 sysdeps/riscv/multiarch/cpu_relax.c > create mode 100644 sysdeps/riscv/multiarch/cpu_relax_impl.S > > diff --git a/sysdeps/riscv/multiarch/Makefile b/sysdeps/riscv/multiarch/M= akefile > index 9f22e31b99..b5b9fcf986 100644 > --- a/sysdeps/riscv/multiarch/Makefile > +++ b/sysdeps/riscv/multiarch/Makefile > @@ -17,3 +17,8 @@ sysdep_routines +=3D \ > strncmp_generic \ > strncmp_zbb > endif > + > +# nscd uses atomic_spin_nop which in turn requires cpu_relax > +ifeq ($(subdir),nscd) > +routines +=3D cpu_relax cpu_relax_impl > +endif > diff --git a/sysdeps/riscv/multiarch/cpu_relax.c b/sysdeps/riscv/multiarc= h/cpu_relax.c > new file mode 100644 > index 0000000000..4e6825ca50 > --- /dev/null > +++ b/sysdeps/riscv/multiarch/cpu_relax.c > @@ -0,0 +1,36 @@ > +/* CPU strand yielding for busy loops. RISC-V version. > + Copyright (C) 2022 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include > +#include > + > +void __cpu_relax (void); > +extern void __cpu_relax_zawrs (void); > +extern void __cpu_relax_zihintpause (void); > + > +static void > +__cpu_relax_generic (void) > +{ > +} > + > +libc_ifunc (__cpu_relax, > + HAVE_RV(zawrs) > + ? __cpu_relax_zawrs > + : HAVE_RV(zihintpause) > + ? __cpu_relax_zihintpause > + : __cpu_relax_generic); > diff --git a/sysdeps/riscv/multiarch/cpu_relax_impl.S b/sysdeps/riscv/mul= tiarch/cpu_relax_impl.S > new file mode 100644 > index 0000000000..5d349c351f > --- /dev/null > +++ b/sysdeps/riscv/multiarch/cpu_relax_impl.S > @@ -0,0 +1,40 @@ > +/* Copyright (C) 2022 Free Software Foundation, Inc. > + > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library. If not, see > + . */ > + > +#include > +#include > + > +.option push > +.option arch,+zawrs > + > +ENTRY_ALIGN (__cpu_relax_zawrs, 4) > + wrs.sto > + ret > +END (__cpu_relax_zawrs) > + > +.option pop > + > +.option push > +.option arch,+zihintpause > + > +ENTRY_ALIGN (__cpu_relax_zihintpause, 4) > + pause > + ret > +END (__cpu_relax_zihintpause) > + > +.option pop > diff --git a/sysdeps/unix/sysv/linux/riscv/atomic-machine.h b/sysdeps/uni= x/sysv/linux/riscv/atomic-machine.h > index dbf70d8d57..88aa58ef95 100644 > --- a/sysdeps/unix/sysv/linux/riscv/atomic-machine.h > +++ b/sysdeps/unix/sysv/linux/riscv/atomic-machine.h > @@ -178,4 +178,7 @@ > # error "ISAs that do not subsume the A extension are not supported" > #endif /* !__riscv_atomic */ > > +extern void __cpu_relax (void); > +#define atomic_spin_nop() __cpu_relax() > + > #endif /* bits/atomic.h */ > -- > 2.39.1 >