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[209.85.210.48]) by smtp.gmail.com with ESMTPSA id r36sm874167otv.68.2021.11.09.11.31.00 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Nov 2021 11:31:00 -0800 (PST) Received: by mail-ot1-f48.google.com with SMTP id x19-20020a9d7053000000b0055c8b39420bso300909otj.1 for ; Tue, 09 Nov 2021 11:31:00 -0800 (PST) X-Received: by 2002:a9d:e8c:: with SMTP id 12mr7829567otj.105.1636486260598; Tue, 09 Nov 2021 11:31:00 -0800 (PST) MIME-Version: 1.0 References: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> In-Reply-To: From: Andrew Waterman Date: Tue, 9 Nov 2021 11:30:49 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC patch 0/5] RISC-V: Add vector ISA support To: Vincent Chen , libc-alpha@sourceware.org, Palmer Dabbelt , DJ Delorie , Andrew Waterman Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Nov 2021 19:31:06 -0000 On Tue, Nov 9, 2021 at 11:21 AM Darius Rad wrote: > > On Mon, Sep 13, 2021 at 09:41:13AM +0800, Vincent Chen wrote: > > This patchset adds required ports to support RISC-V Vector (RVV) extension. > > > > Since the length of the vector register in RVV (the theoretical maximum > > is 2^XLEN-1 bits) is variable, a huge and flexible space is needed to back > > up all vector registers in the signal context. This patchset expands the > > default SIGSTKSZ, MINSIGSTKSZ, and PTHREAD_STACK_MIN to ensure the stack > > size is enough for the normal case (VLENB <= 128 bytes). Linux kernel also > > places the exact minimum signal stack size in AT_MINSIGSTKSZ entry of the > > auxiliary vector to inform user, so user still can know the sutible minimum > > signal stack size by sysconf (_SC_MINSIGSTKSZ) if the VLENB is greater > > than 128 bytes. > > > > In addition, according to the specification, the VCSR that combines VXRM and > > VXSAT has thread storage duration, so this patchset adds the required user > > context operation for it. > > > > Finally, the RISC-V glibc customized sigcontext.h has been removed in this > > patchset. to reduce the synchronization work when new extension support is > > introduced to the Linux environment. However, it may bring some backward > > incompatible issues. Therefore, I sent an RFC patch > > (https://sourceware.org/pipermail/libc-alpha/2020-June/115549.html) > > to discuss this modification before this patchset. As I mentioned in the > > RFC patch thread, I used OpenEmbeded to evaluate the impact. During the > > tests, I didn't get any compiler errors. Therefore, I infer that this > > modification may not cause server backward incompatible issues at this > > moment. > > > > 1. The RISC-V V-extension draft v1.0 can be found in > > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc > > 2. The associated kernel implementation can be found in > > http://lists.infradead.org/pipermail/linux-riscv/2021-September/008249.html > > 3. QEMU with RISC-V V-extension support can be found in > > https://github.com/sifive/qemu/tree/rvv-1.0 > > > > For the record on libc-alpha, I object to these changes. In particular, > the lack of a user space API for the corresponding Linux support. More > discussion on linux-riscv: > > https://lists.infradead.org/pipermail/linux-riscv/2021-September/thread.html#8361 I do not agree with that analysis. The vector extension scales down to having potentially very little state (512 bytes on RV64) and we expect typical applications-processor implementations to land in the 512 - 2048-byte range. This matches AVX, not AMX. Furthermore, we want all implementations to take advantage of vectorized C string/memory functions without having to explicitly opt in. Not doing this would put RISC-V at a significant competitive disadvantage vs. other architectures with SIMD units. > > > > Vincent Chen (5): > > RISC-V: Remove riscv-specific sigcontext.h > > RISC-V: Reserve about 5K space in mcontext_t to support future ISA > > expansion. > > RISC-V: Save and restore VCSR when doing user context switch > > RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers > > RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment > > > > sysdeps/riscv/Makefile | 5 +++ > > sysdeps/riscv/rtld-global-offsets.sym | 7 ++++ > > sysdeps/unix/sysv/linux/riscv/bits/hwcap.h | 31 ++++++++++++++++ > > .../unix/sysv/linux/riscv/bits/pthread_stack_min.h | 21 +++++++++++ > > sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h | 31 ---------------- > > sysdeps/unix/sysv/linux/riscv/bits/sigstack.h | 32 +++++++++++++++++ > > sysdeps/unix/sysv/linux/riscv/getcontext.S | 22 +++++++++++- > > sysdeps/unix/sysv/linux/riscv/setcontext.S | 22 ++++++++++++ > > sysdeps/unix/sysv/linux/riscv/swapcontext.S | 41 ++++++++++++++++++++++ > > sysdeps/unix/sysv/linux/riscv/sys/ucontext.h | 2 ++ > > .../sysv/linux/riscv/sysconf-pthread_stack_min.h | 39 ++++++++++++++++++++ > > sysdeps/unix/sysv/linux/riscv/sysdep.h | 1 + > > sysdeps/unix/sysv/linux/riscv/ucontext_i.sym | 6 ++++ > > 13 files changed, 228 insertions(+), 32 deletions(-) > > create mode 100644 sysdeps/riscv/rtld-global-offsets.sym > > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/hwcap.h > > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/pthread_stack_min.h > > delete mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h > > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigstack.h > > create mode 100644 sysdeps/unix/sysv/linux/riscv/sysconf-pthread_stack_min.h > > > > -- > > 2.7.4 > >