From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by sourceware.org (Postfix) with ESMTPS id 42EF13858D1E for ; Tue, 7 Feb 2023 00:29:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 42EF13858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-wm1-x32a.google.com with SMTP id k8-20020a05600c1c8800b003dc57ea0dfeso12062517wms.0 for ; Mon, 06 Feb 2023 16:29:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=LVVK5M487sOXZT+7BFy33wtswditas4/I7/r8nDhUmI=; b=DgCJEd+R+VZf/Vt8zATHDVCwcfb6uulwQKKIYgoyFatOX8TjLco2OcbHU/EGF5Vaj0 Vjwqz27qCaTbReGfDfbMDJ2Fg9fXmKfpBMFS5ddd9mU1o33dVuJWyCga6/o6cjJeqPB2 bYc8X21/7FH4bEbKhNMOrDkzG/1uLIvuhKI5FEWc+DxihdXkWTZR65tKynICfK74qMgC ebRlBx69S0nVDPMl8qfmt8YyDP9eXObyekC2xeOekM0bOrO9kwI3kcv5IvPqOxMBwjSD bc6UbvwlCKgx7ukiQyIZE5wRpjQRqBudO2CQdwIMy9ccCrDaRG2FbLDb7+M9/H8uP9Qv 66kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=LVVK5M487sOXZT+7BFy33wtswditas4/I7/r8nDhUmI=; b=3yyKfQglxHUByl0thqFb42S1FpzbsZJe6CdtPhkeYMo+z8BOpUgY4aQ99+o2X2HHCR hTOmM6AXarPZ7C9+xN3Rkd6YcTu4P0WDUIEWqtweCAdhlxTjL/QXlT2ZBGZia4EnWzAj 52NnQz9dGKLjgQ1Pc+rqkn4Kqaq8f+egPMQ/rHzlfNQDH+MQ9sQ4z7i2L2Z4OfQBisLR n1vGSLXXjFmNRcJMmg5WLIZyNrq7iuEjiD3hQa/AelvAp7lGsTZqgwxOqWCajTHuloOD Eh8XIlGxkc/IsGv9Y6ez7w4YujbbRWsdaAH+8RYaTadLTvYZM75ZwUfH8kMEV8bdFTAk DrPw== X-Gm-Message-State: AO0yUKUKfGsBnsGqCxUJx2tA/9RmyZWkCbFE8VOlNslgvZXZnBJRqeFL iqMS7wdy5WAJP0d0+P2+hQbmGPdHsBockkzAFHD1Ig== X-Google-Smtp-Source: AK7set/5mRTaLkFGS8DzeqReGX5rXMA8tJc1E8tFnL9Nv2PYsjHpfP/afLaVF15lM0IKveHCr0GseWVuJ1dc9pJppkE= X-Received: by 2002:a7b:c2e8:0:b0:3d0:1489:78c4 with SMTP id e8-20020a7bc2e8000000b003d0148978c4mr1239169wmk.167.1675729767126; Mon, 06 Feb 2023 16:29:27 -0800 (PST) MIME-Version: 1.0 References: <20230207001618.458947-1-christoph.muellner@vrull.eu> <20230207001618.458947-20-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Tue, 7 Feb 2023 01:29:13 +0100 Message-ID: Subject: Re: [RFC PATCH 19/19] riscv: Add __riscv_cpu_relax() to allow yielding in busy loops To: Andrew Waterman Cc: libc-alpha@sourceware.org, Palmer Dabbelt , Darius Rad , DJ Delorie , Vineet Gupta , Kito Cheng , Jeff Law , Philipp Tomsich , Heiko Stuebner Content-Type: multipart/alternative; boundary="000000000000826deb05f4113d03" X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000826deb05f4113d03 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 7, 2023 at 1:23 AM Andrew Waterman wrote: > Note that all implementations must support `pause`, since it's a HINT > instruction encoded within a base-ISA instruction that has no > architecturally visible effect. So it's not clear to me that there's > any virtue in distinguishing implementations that claim to support > Zihintpause from those that don't. > Will be considered in a v2. Thanks! > > > On Mon, Feb 6, 2023 at 4:17 PM Christoph Muellner > wrote: > > > > From: Christoph M=C3=BCllner > > > > The spinning loop of PTHREAD_MUTEX_ADAPTIVE_NP provides the hook > > atomic_spin_nop() that can be used by architectures. > > > > On RISC-V we have two instructions that can be used here: > > * WRS.STO from the Zawrs extension > > * PAUSE from the Zihintpause extension > > > > Let's use these instructions and prefer WRS.STO over PAUSE > > (based on availability of the corresponding ISA extension > > at runtime). > > > > Signed-off-by: Christoph M=C3=BCllner > > --- > > sysdeps/riscv/multiarch/Makefile | 5 +++ > > sysdeps/riscv/multiarch/cpu_relax.c | 36 +++++++++++++++++ > > sysdeps/riscv/multiarch/cpu_relax_impl.S | 40 +++++++++++++++++++ > > .../unix/sysv/linux/riscv/atomic-machine.h | 3 ++ > > 4 files changed, 84 insertions(+) > > create mode 100644 sysdeps/riscv/multiarch/cpu_relax.c > > create mode 100644 sysdeps/riscv/multiarch/cpu_relax_impl.S > > > > diff --git a/sysdeps/riscv/multiarch/Makefile > b/sysdeps/riscv/multiarch/Makefile > > index 9f22e31b99..b5b9fcf986 100644 > > --- a/sysdeps/riscv/multiarch/Makefile > > +++ b/sysdeps/riscv/multiarch/Makefile > > @@ -17,3 +17,8 @@ sysdep_routines +=3D \ > > strncmp_generic \ > > strncmp_zbb > > endif > > + > > +# nscd uses atomic_spin_nop which in turn requires cpu_relax > > +ifeq ($(subdir),nscd) > > +routines +=3D cpu_relax cpu_relax_impl > > +endif > > diff --git a/sysdeps/riscv/multiarch/cpu_relax.c > b/sysdeps/riscv/multiarch/cpu_relax.c > > new file mode 100644 > > index 0000000000..4e6825ca50 > > --- /dev/null > > +++ b/sysdeps/riscv/multiarch/cpu_relax.c > > @@ -0,0 +1,36 @@ > > +/* CPU strand yielding for busy loops. RISC-V version. > > + Copyright (C) 2022 Free Software Foundation, Inc. > > + This file is part of the GNU C Library. > > + > > + The GNU C Library is free software; you can redistribute it and/or > > + modify it under the terms of the GNU Lesser General Public > > + License as published by the Free Software Foundation; either > > + version 2.1 of the License, or (at your option) any later version. > > + > > + The GNU C Library is distributed in the hope that it will be useful, > > + but WITHOUT ANY WARRANTY; without even the implied warranty of > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + Lesser General Public License for more details. > > + > > + You should have received a copy of the GNU Lesser General Public > > + License along with the GNU C Library; if not, see > > + . */ > > + > > +#include > > +#include > > + > > +void __cpu_relax (void); > > +extern void __cpu_relax_zawrs (void); > > +extern void __cpu_relax_zihintpause (void); > > + > > +static void > > +__cpu_relax_generic (void) > > +{ > > +} > > + > > +libc_ifunc (__cpu_relax, > > + HAVE_RV(zawrs) > > + ? __cpu_relax_zawrs > > + : HAVE_RV(zihintpause) > > + ? __cpu_relax_zihintpause > > + : __cpu_relax_generic); > > diff --git a/sysdeps/riscv/multiarch/cpu_relax_impl.S > b/sysdeps/riscv/multiarch/cpu_relax_impl.S > > new file mode 100644 > > index 0000000000..5d349c351f > > --- /dev/null > > +++ b/sysdeps/riscv/multiarch/cpu_relax_impl.S > > @@ -0,0 +1,40 @@ > > +/* Copyright (C) 2022 Free Software Foundation, Inc. > > + > > + This file is part of the GNU C Library. > > + > > + The GNU C Library is free software; you can redistribute it and/or > > + modify it under the terms of the GNU Lesser General Public > > + License as published by the Free Software Foundation; either > > + version 2.1 of the License, or (at your option) any later version. > > + > > + The GNU C Library is distributed in the hope that it will be useful, > > + but WITHOUT ANY WARRANTY; without even the implied warranty of > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + Lesser General Public License for more details. > > + > > + You should have received a copy of the GNU Lesser General Public > > + License along with the GNU C Library. If not, see > > + . */ > > + > > +#include > > +#include > > + > > +.option push > > +.option arch,+zawrs > > + > > +ENTRY_ALIGN (__cpu_relax_zawrs, 4) > > + wrs.sto > > + ret > > +END (__cpu_relax_zawrs) > > + > > +.option pop > > + > > +.option push > > +.option arch,+zihintpause > > + > > +ENTRY_ALIGN (__cpu_relax_zihintpause, 4) > > + pause > > + ret > > +END (__cpu_relax_zihintpause) > > + > > +.option pop > > diff --git a/sysdeps/unix/sysv/linux/riscv/atomic-machine.h > b/sysdeps/unix/sysv/linux/riscv/atomic-machine.h > > index dbf70d8d57..88aa58ef95 100644 > > --- a/sysdeps/unix/sysv/linux/riscv/atomic-machine.h > > +++ b/sysdeps/unix/sysv/linux/riscv/atomic-machine.h > > @@ -178,4 +178,7 @@ > > # error "ISAs that do not subsume the A extension are not supported" > > #endif /* !__riscv_atomic */ > > > > +extern void __cpu_relax (void); > > +#define atomic_spin_nop() __cpu_relax() > > + > > #endif /* bits/atomic.h */ > > -- > > 2.39.1 > > > --000000000000826deb05f4113d03--