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J . Lu" , Sajan Karumanchi , bmerry@sarao.ac.za, pmallapp@amd.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Feb 6, 2024 at 5:43=E2=80=AFPM Adhemerval Zanella wrote: > > For AMD Zen3+ architecture, the performance of the vectorized loop is > slightly better than ERMS. > > Checked on x86_64-linux-gnu on Zen3. > --- > sysdeps/x86/dl-cacheinfo.h | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > index 74b804c5e6..f2cd6f179d 100644 > --- a/sysdeps/x86/dl-cacheinfo.h > +++ b/sysdeps/x86/dl-cacheinfo.h > @@ -1010,11 +1010,17 @@ dl_init_cacheinfo (struct cpu_features *cpu_featu= res) > if (tunable_size > minimum_rep_movsb_threshold) > rep_movsb_threshold =3D tunable_size; > > - /* NB: The default value of the x86_rep_stosb_threshold tunable is the > - same as the default value of __x86_rep_stosb_threshold and the > - minimum value is fixed. */ > - rep_stosb_threshold =3D TUNABLE_GET (x86_rep_stosb_threshold, > - long int, NULL); > + /* For AMD Zen3+ architecture, the performance of the vectorized loop = is > + slightly better than ERMS. */ > + if (cpu_features->basic.kind =3D=3D arch_kind_amd) > + rep_stosb_threshold =3D SIZE_MAX; > + > + if (TUNABLE_IS_INITIALIZED (x86_rep_stosb_threshold)) > + /* NB: The default value of the x86_rep_stosb_threshold tunable is t= he > + same as the default value of __x86_rep_stosb_threshold and the > + minimum value is fixed. */ > + rep_stosb_threshold =3D TUNABLE_GET (x86_rep_stosb_threshold, > + long int, NULL); Can we keep the unconditional rep_stosb_threshold =3D TUNABLE_GET (x86_rep_stosb_threshold, long int, NULL); for targets other than AMD? Its easier to control the defaults that way. > > TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, data, 0, SIZE_MAX); > TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, shared, 0, SIZE_MAX); > -- > 2.34.1 >