From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by sourceware.org (Postfix) with ESMTPS id 9E48F385E02B for ; Mon, 3 Oct 2022 21:11:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9E48F385E02B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x530.google.com with SMTP id a13so16333779edj.0 for ; Mon, 03 Oct 2022 14:11:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=ry05aM6LqAloJE/5JRfTyE4xXA6m50XpHdHPZOk4yIU=; b=DGlAnIKeOzG3kEWb4UlseECo9CbnpwSS00wEtDSxyi7r77Nx48m+Jo9RpGQvX0N21H 7GlOILzj8oijzH+ySTO2Pfn6rrR3sW7SWDOlaxIn3KqM3kvDAgr0Q5+qNnrGUYb2bB95 vgdbUfO2zFj3/ad0HBXOvqsClP4np9b6abMy4pG5u+XiEXS4UGNKBYFdV/yKMz6e9S/C C1s7bPRbqJX7qnxVBnG4H09DCMWj8KrM8qpjlYXxU1MpCwnEf7zrrBdVUOomJiSchGtP TzfibCV1lMGkN4r/ReHmigRYlditCHoB/GrkhBuiY9X+aAnqTK9Ci3jqPAH4cqQm2OHm nf3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=ry05aM6LqAloJE/5JRfTyE4xXA6m50XpHdHPZOk4yIU=; b=OsJ7GJ4Lg8YnY0AmlPDO0M4sIJhxpVRcKDP0QVzbWTch6Ti8idEZxEXEetkw1pM0K0 wrk9D31vy+4q8LSXoZoewKVaaHq/de2CDh55JJpnyLqpVPPhJ+Z6lQM11lkixZn4Bh1p YKOe5o0AC5FPIkur0U1D+zdGHqcadHo1yy9xQjFpdI0zAwfVMqZTn/JQ9agdDJiFJnO5 Hc5Q/bcSwo6/GE7GefSXLZTdxKgso6610VeWNq+WlkeRimuzb23pofethjT9zAu23tC6 GyDit8dUcOYhuQfdaDRVF/e9OnkvXo74YTJt8KmnAMg3aXfGhZV3zJCCeLnLEZBpU5N/ S7aw== X-Gm-Message-State: ACrzQf1a4TH/krOxzjLgrmeMbkJExWA35pysklSZRvgblJAjyxBiMvVr MYmMpZtc+TYk3kbd0cOSuTvaJdpYp0zJQF4mkcyFAYtuj6o= X-Google-Smtp-Source: AMsMyM5U1JsxHuRwuVF4G9cFFiQD7JSnaHNgMfyBpuZji/LW5I2ex9qao+4ZMr2uERNw39h5sRBTxFOZdP2oADNs5uo= X-Received: by 2002:a05:6402:3584:b0:458:d3fa:fb89 with SMTP id y4-20020a056402358400b00458d3fafb89mr9207607edc.218.1664831509468; Mon, 03 Oct 2022 14:11:49 -0700 (PDT) MIME-Version: 1.0 References: <20221003195944.3274548-1-aurelien@aurel32.net> <20221003195944.3274548-5-aurelien@aurel32.net> In-Reply-To: <20221003195944.3274548-5-aurelien@aurel32.net> From: Noah Goldstein Date: Mon, 3 Oct 2022 14:11:37 -0700 Message-ID: Subject: Re: [PATCH v3 4/8] x86-64: Require BMI2 for AVX2 strncmp implementation To: Aurelien Jarno Cc: libc-alpha@sourceware.org, "H . J . Lu" , Sunil K Pandey Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Oct 3, 2022 at 12:59 PM Aurelien Jarno wrote: > > The AVX2 strncmp implementations uses the 'bzhi' instruction, which > belongs to the BMI2 CPU feature. > > NB: It also uses the 'tzcnt' BMI1 instruction, but it is executed as BSF > as BSF if the CPU doesn't support TZCNT, and produces the same result > for non-zero input. > > Partially fixes: b77b06e0e296 ("x86: Optimize strcmp-avx2.S") > Partially resolves: BZ #29611 > --- > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 7 +++++-- > sysdeps/x86_64/multiarch/strncmp.c | 4 ++-- > 2 files changed, 7 insertions(+), 4 deletions(-) > > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > index a42b0a4620..aebef3daaf 100644 > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > @@ -1176,13 +1176,16 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > IFUNC_IMPL (i, name, strncmp, > X86_IFUNC_IMPL_ADD_V4 (array, i, strncmp, > (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW)), > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (BMI2)), > __strncmp_evex) > X86_IFUNC_IMPL_ADD_V3 (array, i, strncmp, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2)), > __strncmp_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, strncmp, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > && CPU_FEATURE_USABLE (RTM)), > __strncmp_avx2_rtm) > X86_IFUNC_IMPL_ADD_V2 (array, i, strncmp, > diff --git a/sysdeps/x86_64/multiarch/strncmp.c b/sysdeps/x86_64/multiarch/strncmp.c > index 4ebe4bde30..c4f8b6bbb5 100644 > --- a/sysdeps/x86_64/multiarch/strncmp.c > +++ b/sysdeps/x86_64/multiarch/strncmp.c > @@ -41,12 +41,12 @@ IFUNC_SELECTOR (void) > const struct cpu_features *cpu_features = __get_cpu_features (); > > if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2) > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2) > && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, > AVX_Fast_Unaligned_Load, )) > { > if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) > - && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) > - && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)) > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW)) > return OPTIMIZE (evex); > > if (CPU_FEATURE_USABLE_P (cpu_features, RTM)) > -- > 2.35.1 > LGTM. Reviewed-by: Noah Goldstein