From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id A13133857C4C for ; Tue, 18 Jan 2022 19:55:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A13133857C4C Received: by mail-pl1-x62a.google.com with SMTP id u11so20247292plh.13 for ; Tue, 18 Jan 2022 11:55:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kdSEmtxJFXmL6jSXRGS/hCYLlmh4aIKj8c/MbenwnAU=; b=DWWZ2TK10zULDaK7ODbhrsE4lRvre5jEVCJDanUhyD+SWCg55t04rGgm96TP/XcDpC EQYnsUFelvmIN5vZraL8uxhyq6rDqTD624Z3j/yuYJr9KCJb+mUJcBZOn6yVXQs4gvqa Vuua1NZv82QKJyhqNc5ctA7K9yrq/6nG3Xfhc2Xiar9AY1M/HGbKV7Rjsk/0oqC5Nq+C utSx6wDzyLqn6FrZ1CEq/MQi96V+x3YZm9u2157rwEZtb2vbluxCG2pcdGK3/XVLs3Tn MwiA4iW9rkFpgml49JkI/WTLAoXCcii38BSsweHzm3iP0uv7mVEc1zTGWxgQI2fUL7tp h5Xg== X-Gm-Message-State: AOAM532Bu/40aH8V6jlcREiWPSwh4aAMjWuRXMKf4ieJk1+Ve9lN5AHh m1NZIQSqU6FUX01afXdNNhRPG4w6eRwAIjisaViOxJVf X-Google-Smtp-Source: ABdhPJw30JmlyLGX7i3rxBIdNDm/fa6X6e2biEx2veDVIUKgjixVp2vPlqTdSFKOvQ8bit22ZNbNW4hW/IqVySMc4v4= X-Received: by 2002:a17:902:ce86:b0:14a:b9c2:4e36 with SMTP id f6-20020a170902ce8600b0014ab9c24e36mr11770229plg.57.1642535741741; Tue, 18 Jan 2022 11:55:41 -0800 (PST) MIME-Version: 1.0 References: <20220118164238.3761164-1-hjl.tools@gmail.com> In-Reply-To: <20220118164238.3761164-1-hjl.tools@gmail.com> From: Noah Goldstein Date: Tue, 18 Jan 2022 13:55:30 -0600 Message-ID: Subject: Re: [PATCH] x86: Black list more Intel CPUs for TSX [BZ #27398] To: "H.J. Lu" Cc: GNU C Library Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Jan 2022 19:55:44 -0000 On Tue, Jan 18, 2022 at 10:43 AM H.J. Lu via Libc-alpha wrote: > > Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in: > > https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html > > This fixes BZ #27398. > --- > sysdeps/x86/cpu-features.c | 35 ++++++++++++++++++++++++++++++++--- > 1 file changed, 32 insertions(+), 3 deletions(-) > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > index 772ccf8e91..034d9feff7 100644 > --- a/sysdeps/x86/cpu-features.c > +++ b/sysdeps/x86/cpu-features.c > @@ -507,11 +507,40 @@ init_cpu_features (struct cpu_features *cpu_features) > break; > } > > - /* Disable TSX on some Haswell processors to avoid TSX on kernels that > - weren't updated with the latest microcode package (which disables > - broken feature by default). */ > + /* Disable TSX on some processors to avoid TSX on kernels that > + weren't updated with the latest microcode package (which > + disables broken feature by default). */ > switch (model) > { > + case 0x55: > + if (stepping <= 5) > + goto disable_tsx; > + break; > + case 0x8e: > + /* NB: The errata says that only 0xb stepping or lower are > + impacted. But 0xc stepping also exhibits the similar > + behavior. */ Do you have any link for this or is this just from internal testing? > + if (stepping <= 0xc) > + goto disable_tsx; If you want you could make `case 0x8e` fall through into `case 0x9e` given that both disable for `stepping <= 0xc`. This isn't a critical path and clarity might be more important, especially since the `case 0x8e` goes against documentation. > + break; > + case 0x9e: > + if (stepping > 0xc) > + break; > + /* Fall through. */ > + case 0x4e: > + case 0x5e: > + { > + /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for > + processors listed in: > + > +https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html > + */ > +disable_tsx: > + CPU_FEATURE_UNSET (cpu_features, HLE); > + CPU_FEATURE_UNSET (cpu_features, RTM); > + CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT); > + } > + break; > case 0x3f: > /* Xeon E7 v3 with stepping >= 4 has working TSX. */ > if (stepping >= 4) > -- > 2.34.1 > LGTM although have a few comments.