From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id A20D73858430 for ; Sat, 1 Oct 2022 22:30:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A20D73858430 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x635.google.com with SMTP id rk17so15614295ejb.1 for ; Sat, 01 Oct 2022 15:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=zB4GKUO11WfVEStNEW1ncB05aVqBMmbnwxXuoyfO+a8=; b=pn9fqlKtRjJfG0/9nEY8bIb0EBuyPuDUK9Ps5eD6xALZyN6hiUt7pNZMQuQjzRmXmu T4zzJ+fSejsedTNwx266PyiJhISABZxThuLbIdmdPMbrdB5GPq037eSsV8ENXqJwBmIH /CX2MMbOqr4L6faALxmDItOpH/BEWjq4gMvQKeZce9TQNFoDvSx/sLsBrGofLvC1Uie9 zud5oeLST3bQcwg6gW4tjQpbmMLrH7KoLWvp1pIzdEBnQR3AnFZ27Vf9CzODq+iqsBuA hTptb2xF7572g0wOVIaONjw1RsDrCfVZ1022CHsefYH9GmxyOSEbq0FXsfhcx2/Mc3Io ukGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=zB4GKUO11WfVEStNEW1ncB05aVqBMmbnwxXuoyfO+a8=; b=A+0vxPs8D/WpCSfca8A2GDy7AN4btmu2ZoqxFy3q3k23ayzvuBkan1Ev8VXD2SgMKv f0b6Vll9a3Dl6f1rZoDsSOaCaBSzg4Q3XWqN2Jdup0ijIpSFGUZlFBUQ0yBnXGFyealh NSgFh2439xPZ3TtiEhx1lm154Vixn07k/P7RAe8vM3Gtcdc6pu08Uu8xR+5cLUi9KzlE 2qOyqSs/ZvpCYOZiPPmNgkJDu1mBA8mjC76YA0toaWso3JXcWUbsB4CHn7y3cmwcwXkn gf63vWcy9cl7TtQZn6EyyMfuGLZaH+hv2F7GjNjDCtr1IZw785TMl6nijO0KBjKk/dxe kqJw== X-Gm-Message-State: ACrzQf0Ni2x634Bb6QO6aj4HPqXjKAM0zGP+AodHbksDOMAjBYGOpzQH BaGwgY9F8xZYQ1aQOzpTIPzrkRuVdvRSi2JM0/M= X-Google-Smtp-Source: AMsMyM7gTVrD7DKmBSTokns616O9EVmL8GA6tesoHOEKvBv7J1kEfFaNBn3vfdisYHFvPycIiSXBXy4uLNV9SCpcj+c= X-Received: by 2002:a17:906:2bc7:b0:72f:dc70:a3c6 with SMTP id n7-20020a1709062bc700b0072fdc70a3c6mr10830437ejg.645.1664663428438; Sat, 01 Oct 2022 15:30:28 -0700 (PDT) MIME-Version: 1.0 References: <20221001190911.2994478-1-aurelien@aurel32.net> <20221001190911.2994478-5-aurelien@aurel32.net> In-Reply-To: <20221001190911.2994478-5-aurelien@aurel32.net> From: Noah Goldstein Date: Sat, 1 Oct 2022 15:30:16 -0700 Message-ID: Subject: Re: [PATCH 4/4] x86-64: Require LZCNT for AVX2 memrchr implementation To: Aurelien Jarno Cc: libc-alpha@sourceware.org, "H . J . Lu" , Sunil K Pandey Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, Oct 1, 2022 at 12:09 PM Aurelien Jarno wrote: > > The AVX2 memrchr implementation uses the lzcntl and lzcntq instructions, > which belongs to the LZCNT CPU feature. > > Fixes: af5306a735eb ("x86: Optimize memrchr-avx2.S") > Partially resolves: BZ #29611 > --- > sysdeps/x86_64/multiarch/ifunc-avx2.h | 1 + > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 7 +++++-- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/sysdeps/x86_64/multiarch/ifunc-avx2.h b/sysdeps/x86_64/multiarch/ifunc-avx2.h > index a57a9952f3..f1741083fd 100644 > --- a/sysdeps/x86_64/multiarch/ifunc-avx2.h > +++ b/sysdeps/x86_64/multiarch/ifunc-avx2.h > @@ -37,6 +37,7 @@ IFUNC_SELECTOR (void) > > if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2) > && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2) > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, LZCNT) This causes a build failure. Need a corresponding macro in sysdeps/x86/isa-level.h Something like: #define LZCNT_X86_ISA_LEVEL 3 after the BMI2 one. > && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, > AVX_Fast_Unaligned_Load, )) > { > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > index c628462d47..db5a2032d6 100644 > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > @@ -209,13 +209,16 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > IFUNC_IMPL (i, name, memrchr, > X86_IFUNC_IMPL_ADD_V4 (array, i, memrchr, > (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW)), > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (LZCNT)), > __memrchr_evex) > X86_IFUNC_IMPL_ADD_V3 (array, i, memrchr, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (LZCNT)), > __memrchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, memrchr, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (LZCNT) > && CPU_FEATURE_USABLE (RTM)), > __memrchr_avx2_rtm) > /* ISA V2 wrapper for SSE2 implementation because the SSE2 > -- > 2.35.1 >