From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1130.google.com (mail-yw1-x1130.google.com [IPv6:2607:f8b0:4864:20::1130]) by sourceware.org (Postfix) with ESMTPS id 8C9D9383577A for ; Tue, 28 Jun 2022 04:07:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8C9D9383577A Received: by mail-yw1-x1130.google.com with SMTP id 00721157ae682-317741c86fdso104402377b3.2 for ; Mon, 27 Jun 2022 21:07:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nbUXSvjOr/Jo8Bnab0wG4AOaCZ/q3Xh3T1phktLY/88=; b=HKpjHS+tCmPmQgE1JLQkU/QRyi61S/dYcEH/Sk18JBSOLG5hH2u+Q8vW4tYhNyhxWL ZpNg61P7PKkEoxjs+tWHRexvmy482Mwaw0gB1m8CucstoklT0T3/rYzDw23vizxp2ndl cxbN0+H3n8L+5EJMnl/0UvboKO+y6JIefhDx83hJEGxwt7pzNgIOzpEBBk5VYQa8TEph Y04ut6IfQ9O0kAPqyFfTPZGUxeAKZ+ktaqCTsbYTOpSEVnAaGGYgwqyaW1FqPymB6buA nsSs8HWg0xKFKriJ7VfRAkutIkdWSIa8iv88CPEM7+sf6gdgXjaGwIEeRyVsds4InPOv Qq3w== X-Gm-Message-State: AJIora8gwptPTxlbkOMONzI+p/frSxhvRDnaKT4JkZubBmH4fPzA8mss S8Pgx7Z4YT218mH94p/iE4E+SgkU77vAR2709hI= X-Google-Smtp-Source: AGRyM1sVptrIqpDhr5bCO0p/mfsDw31yOswdpBpu+szOB3LH33AlxXwcdhFrK7H3FTZlXxfHsdugZilRsI35WJhZl6I= X-Received: by 2002:a0d:ebc4:0:b0:318:31c1:be92 with SMTP id u187-20020a0debc4000000b0031831c1be92mr19686125ywe.422.1656389242981; Mon, 27 Jun 2022 21:07:22 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> <20220628034939.2116112-1-goldstein.w.n@gmail.com> In-Reply-To: From: Noah Goldstein Date: Mon, 27 Jun 2022 21:07:12 -0700 Message-ID: Subject: Re: [PATCH v4] x86: Add more feature definitions to isa-level.h To: "H.J. Lu" Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 04:07:24 -0000 On Mon, Jun 27, 2022 at 8:59 PM H.J. Lu wrote: > > On Mon, Jun 27, 2022 at 8:49 PM Noah Goldstein wrote: > > > > This commit doesn't change anything in itself. It is just to add > > definitions that will be needed by future patches. > > --- > > sysdeps/x86/isa-level.h | 17 +++++++++++++++++ > > 1 file changed, 17 insertions(+) > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > > index f293aea906..2cbce25840 100644 > > --- a/sysdeps/x86/isa-level.h > > +++ b/sysdeps/x86/isa-level.h > > @@ -67,15 +67,29 @@ > > /* Depending on the minimum ISA level, a feature check result can be a > > compile-time constant.. */ > > > > + > > +/* ISA CPU_FEATURE_USABLE_P defaults. */ > > What does "defaults" mean? "For X86_ISA_CPU_FEATURE_USABLE_P"? Done in V5 > > > + > > /* ISA level >= 4 guaranteed includes. */ > > #define AVX512F_X86_ISA_LEVEL 4 > > #define AVX512VL_X86_ISA_LEVEL 4 > > #define AVX512BW_X86_ISA_LEVEL 4 > > +#define AVX512DQ_X86_ISA_LEVEL 4 > > > > /* ISA level >= 3 guaranteed includes. */ > > #define AVX_X86_ISA_LEVEL 3 > > #define AVX2_X86_ISA_LEVEL 3 > > #define BMI2_X86_ISA_LEVEL 3 > > +#define MOVBE_X86_ISA_LEVEL 3 > > + > > +/* ISA level >= 2 guaranteed includes. */ > > +#define SSE4_2_X86_ISA_LEVEL 2 > > +#define SSSE3_X86_ISA_LEVEL 2 > > + > > + > > +/* ISA CPU_FEATURES_ARCH_P defaults. */ > > "For X86_ISA_CPU_FEATURES_ARCH_P"? Done in V5 > > > + > > +/* Isa level >= 3 feature(s) enabled. */ > > No need for this. Some features may be disabled. Done in V5 > > > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > > for the following CPUs: > > @@ -89,6 +103,9 @@ > > when ISA level < 3. */ > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > > > +/* Isa level >= 2 feature(s) enabled. */ > > These are not features in ISAs. "Feature(s) enabled when ISA level >= 2"? Done in V5 > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 > > + > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > > runtime checks. They differ in two ways. > > -- > > 2.34.1 > > > > > -- > H.J.