From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by sourceware.org (Postfix) with ESMTPS id 36E5F3858D1E for ; Tue, 3 Jan 2023 20:24:44 +0000 (GMT) Received: by mail-ed1-x530.google.com with SMTP id i9so45539306edj.4 for ; Tue, 03 Jan 2023 12:24:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=cBYFuIHG6+1GAA8sggOCRzTFfEAtjH+eRABPQcwSr+g=; b=bYdat2WOMSUdDwqYZX6rq8Vs5j3b/ZA0XDGRdyRAz0DQvSar298UhUAg5FaHf+2ap8 4Wf35jEwPBSkE+bJ2tE1coQ3UmAh5zsd9SaobYnRgy1wPXuXw2KM8TA6pe2AW8SvaDzR 1nosYjlVOPqDEAjGIAgvvEClCJEW0+DdOgGY56RtYMFY0VTcbyIwwgPV42DXmW2CzXM8 yP9RdwA5sWaQcL1g71h2EPk6H1t2ga9tSVte/DeKZBHQiKYoQPGJwpfWPufFMS6LD2T1 N7vdi3+dDyzAeZNW6tlLbgVtA/BQgTJY7AnZYKM0E7doJ2NDogjIxMCIfP7lq6yEno3O sPEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=cBYFuIHG6+1GAA8sggOCRzTFfEAtjH+eRABPQcwSr+g=; b=GoQIoCc4s+DrKANQgO/QFtixTT5TiQ7PdEY/J3nweD/wX54NlPbMW1ADhA18pXfVRb qDsRU7lCR1ZEt4BN1gZz1AB/O6+P5TM9bXW17LXeNAopCvnr/0TMBR5rtc3OhYCEyYNh rxSIlIbP1z5LguvLhWgkYRC6cZuf/EPG+Kv0hKbR6y07+ISSD/nGCjGOlNy1JtY+nFoH tnurDC65BvSxYZ/65oj3BVJEYA6ZG5oaUHZAceGz13nyDfxqF0EZHfFD3eZZ+mGwYXlL nZ+23mQakKv/Ik0i72pmNTzBpLztbseczlsWQj4yWYz0KgWk3pTaFF4Rm/7tRGr1kVXc gM0w== X-Gm-Message-State: AFqh2kqSNKMiSTjCzhbY7ie6iQIltJTrHC/RbSNfcrel2vLv686vAenn 2y9FLi/0AddlyRxnq6ZUWEGvYRZVxbSsehyvJ46/Lxww X-Google-Smtp-Source: AMrXdXvBnvOk7KDgvK8KfYb+BbF/m5y4J3ItJKSrLuiBs6qaQkBQWvXxLk0QMDT6+2T82/FZ3VUVKey4SneFrfojdwQ= X-Received: by 2002:a50:cc47:0:b0:461:b6a9:c5cb with SMTP id n7-20020a50cc47000000b00461b6a9c5cbmr5084358edi.148.1672777481861; Tue, 03 Jan 2023 12:24:41 -0800 (PST) MIME-Version: 1.0 References: <20230103193715.2549830-1-hjl.tools@gmail.com> In-Reply-To: <20230103193715.2549830-1-hjl.tools@gmail.com> From: Noah Goldstein Date: Tue, 3 Jan 2023 12:24:31 -0800 Message-ID: Subject: Re: [PATCH] x86: Check the minimum non_temporal_threshold [BZ #29953] To: "H.J. Lu" Cc: libc-alpha@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Jan 3, 2023 at 11:37 AM H.J. Lu wrote: > > The minimum non_temporal_threshold is 0x4040. non_temporal_threshold may > be set to less than the minimum value when the shared cache size isn't > available (e.g., in an emulator) or by the tunable. Add a check for > the minimum non_temporal_threshold. > > This fixes BZ #29953. > --- > sysdeps/x86/dl-cacheinfo.h | 23 ++++++++++++++--------- > 1 file changed, 14 insertions(+), 9 deletions(-) > > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > index e9f3382108..92e8e40752 100644 > --- a/sysdeps/x86/dl-cacheinfo.h > +++ b/sysdeps/x86/dl-cacheinfo.h > @@ -861,8 +861,18 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > share of the cache, it has a substantial risk of negatively > impacting the performance of other threads running on the chip. */ > unsigned long int non_temporal_threshold = shared * 3 / 4; > + /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of > + 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best > + if that operation cannot overflow. Minimum of 0x4040 (16448) because the > + L(large_memset_4x) loops need 64-byte to cache align and enough space for > + at least 1 iteration of 4x PAGE_SIZE unrolled loop. Both values are > + reflected in the manual. */ > + unsigned long int minimum_non_temporal_threshold = 0x4040; > + if (non_temporal_threshold < minimum_non_temporal_threshold) > + non_temporal_threshold = minimum_non_temporal_threshold; > Should we have equivalent logic for max incase shared is somehow > SIZE_MAX / 12? > #if HAVE_TUNABLES > + unsigned long int maximum_non_temporal_threshold = SIZE_MAX >> 4; > /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ > unsigned int minimum_rep_movsb_threshold; > #endif > @@ -915,8 +925,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > shared = tunable_size; > > tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); > - /* NB: Ignore the default value 0. */ > - if (tunable_size != 0) > + if (tunable_size > minimum_non_temporal_threshold > + && tunable_size <= maximum_non_temporal_threshold) > non_temporal_threshold = tunable_size; > > tunable_size = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); > @@ -931,14 +941,9 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > > TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, data, 0, SIZE_MAX); > TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, shared, 0, SIZE_MAX); > - /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of > - 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best > - if that operation cannot overflow. Minimum of 0x4040 (16448) because the > - L(large_memset_4x) loops need 64-byte to cache align and enough space for > - at least 1 iteration of 4x PAGE_SIZE unrolled loop. Both values are > - reflected in the manual. */ > TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, non_temporal_threshold, > - 0x4040, SIZE_MAX >> 4); > + minimum_non_temporal_threshold, > + maximum_non_temporal_threshold); > TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, rep_movsb_threshold, > minimum_rep_movsb_threshold, SIZE_MAX); > TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, rep_stosb_threshold, 1, > -- > 2.39.0 >