From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb34.google.com (mail-yb1-xb34.google.com [IPv6:2607:f8b0:4864:20::b34]) by sourceware.org (Postfix) with ESMTPS id 37F3F3831C9B for ; Tue, 28 Jun 2022 02:42:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 37F3F3831C9B Received: by mail-yb1-xb34.google.com with SMTP id p136so13730591ybg.4 for ; Mon, 27 Jun 2022 19:42:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FtyWbVptIZyf5s79cXQ5sS8pZs/YD5RGMWjHukJJuWY=; b=xp20KwbiPRv5DjaxmHzWt7v1FgsTXO0PWcc6KhtYnXXQxQljO4vAfd1SjKb3Ah2IWU kwKgWRZXYuODcb/UOzGrMkCqF86BXt1IIAPLZsKeykW2JWtwo4FkScE2bAIRJRemuXNm OAP6aHhS+u3yyltNeJDDTD7eJbMOIvDYyd2i9yTyHGt2adMq6Yucq5FHwM46OhOLgvDX tUtgmJK7HaRYq+lfS52GtJ9Zly49lu3MfEYglincVYM9pcuviDp1/GP1LPDaphY894/f PRFINq6iCEXC3+0KsoKdGLKz1r3MVt/gFGBMkh+AOjxUkhOPoQTRqng1sy6RyE08kyDu N9bQ== X-Gm-Message-State: AJIora8rGL+xzcEWu09ShT6c3kRQ3p72CWM24pRvsP+cmFUA5SRmsMZQ 8vBjz1HnAIQMXI3Lo5F0+tYM6qXQOS4ezhv2Rr8= X-Google-Smtp-Source: AGRyM1tuNUbesZQDURVGxanaP4heH6p5s+angL8BvYhAkISWi+QNd3JUp9VGr6wb9hienFjvc2RU8Wi0VxMz1EAxKzM= X-Received: by 2002:a25:b9c3:0:b0:668:a418:13c with SMTP id y3-20020a25b9c3000000b00668a418013cmr17878711ybj.498.1656384128698; Mon, 27 Jun 2022 19:42:08 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> <20220628020342.213807-1-goldstein.w.n@gmail.com> In-Reply-To: From: Noah Goldstein Date: Mon, 27 Jun 2022 19:41:58 -0700 Message-ID: Subject: Re: [PATCH v2] x86: Add more feature definitions to isa-level.h To: "H.J. Lu" Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 02:42:10 -0000 On Mon, Jun 27, 2022 at 7:39 PM H.J. Lu wrote: > > On Mon, Jun 27, 2022 at 7:34 PM Noah Goldstein wrote: > > > > On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu wrote: > > > > > > On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein wrote: > > > > > > > > This commit doesn't change anything in itself. It is just to add > > > > definitions that will be needed by future patches. > > > > --- > > > > sysdeps/x86/isa-level.h | 10 ++++++++++ > > > > 1 file changed, 10 insertions(+) > > > > > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > > > > index f293aea906..024d1deb80 100644 > > > > --- a/sysdeps/x86/isa-level.h > > > > +++ b/sysdeps/x86/isa-level.h > > > > @@ -71,11 +71,13 @@ > > > > #define AVX512F_X86_ISA_LEVEL 4 > > > > #define AVX512VL_X86_ISA_LEVEL 4 > > > > #define AVX512BW_X86_ISA_LEVEL 4 > > > > +#define AVX512DQ_X86_ISA_LEVEL 4 > > > > > > > > /* ISA level >= 3 guaranteed includes. */ > > > > #define AVX_X86_ISA_LEVEL 3 > > > > #define AVX2_X86_ISA_LEVEL 3 > > > > #define BMI2_X86_ISA_LEVEL 3 > > > > +#define MOVBE_X86_ISA_LEVEL 3 > > > > > > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > > > > for the following CPUs: > > > > @@ -89,6 +91,14 @@ > > > > when ISA level < 3. */ > > > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > > > > > > > +/* ISA level >= 2 guaranteed includes. */ > > > > Have a comment for ISA level 2 here. > > ISA is included. But arch features can be enabled/disabled. > > > > > +#define SSE4_2_X86_ISA_LEVEL 2 > > > > +#define SSSE3_X86_ISA_LEVEL 2 > > > > + > > > > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be > > > > + affected by this. */ > > > > > > /* Features enabled when ISA level >= 2. */ > > > > Hm? This is singular. > > Will more be added? None for this patchset. If in the future there are (with the same affected CPU set) I will make the comment plural. > > > > > > > > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 > > > > + > > > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > > > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > > > > runtime checks. They differ in two ways. > > > > -- > > > > 2.34.1 > > > > > > > > > > > > > -- > > > H.J. > > > > -- > H.J.