From: Noah Goldstein <goldstein.w.n@gmail.com>
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: GNU C Library <libc-alpha@sourceware.org>,
"Carlos O'Donell" <carlos@systemhalted.org>
Subject: Re: [PATCH v2] x86: Add more feature definitions to isa-level.h
Date: Mon, 27 Jun 2022 19:34:40 -0700 [thread overview]
Message-ID: <CAFUsyfJ5oWHvf+kzeFPgabkZfM-webQVPjacmdkts1gw0Qar4g@mail.gmail.com> (raw)
In-Reply-To: <CAMe9rOq+TetATekjMHxouz9cSko=0Dbk2KMs_3fTbkDjLchRww@mail.gmail.com>
On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > This commit doesn't change anything in itself. It is just to add
> > definitions that will be needed by future patches.
> > ---
> > sysdeps/x86/isa-level.h | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > index f293aea906..024d1deb80 100644
> > --- a/sysdeps/x86/isa-level.h
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -71,11 +71,13 @@
> > #define AVX512F_X86_ISA_LEVEL 4
> > #define AVX512VL_X86_ISA_LEVEL 4
> > #define AVX512BW_X86_ISA_LEVEL 4
> > +#define AVX512DQ_X86_ISA_LEVEL 4
> >
> > /* ISA level >= 3 guaranteed includes. */
> > #define AVX_X86_ISA_LEVEL 3
> > #define AVX2_X86_ISA_LEVEL 3
> > #define BMI2_X86_ISA_LEVEL 3
> > +#define MOVBE_X86_ISA_LEVEL 3
> >
> > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > for the following CPUs:
> > @@ -89,6 +91,14 @@
> > when ISA level < 3. */
> > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> >
> > +/* ISA level >= 2 guaranteed includes. */
Have a comment for ISA level 2 here.
> > +#define SSE4_2_X86_ISA_LEVEL 2
> > +#define SSSE3_X86_ISA_LEVEL 2
> > +
> > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be
> > + affected by this. */
>
> /* Features enabled when ISA level >= 2. */
Hm? This is singular.
>
> > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > +
> > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > runtime checks. They differ in two ways.
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
next prev parent reply other threads:[~2022-06-28 2:34 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-28 1:04 [PATCH v1] " Noah Goldstein
2022-06-28 1:56 ` H.J. Lu
2022-06-28 2:04 ` Noah Goldstein
2022-06-28 2:03 ` [PATCH v2] " Noah Goldstein
2022-06-28 2:29 ` H.J. Lu
2022-06-28 2:34 ` Noah Goldstein [this message]
2022-06-28 2:38 ` H.J. Lu
2022-06-28 2:41 ` Noah Goldstein
2022-06-28 3:03 ` H.J. Lu
2022-06-28 3:26 ` [PATCH v3] " Noah Goldstein
2022-06-28 3:30 ` H.J. Lu
2022-06-28 3:32 ` H.J. Lu
2022-06-28 3:35 ` Noah Goldstein
2022-06-28 3:44 ` H.J. Lu
2022-06-28 3:50 ` Noah Goldstein
2022-06-28 3:49 ` [PATCH v4] " Noah Goldstein
2022-06-28 3:58 ` H.J. Lu
2022-06-28 4:07 ` Noah Goldstein
2022-06-28 4:07 ` [PATCH v5] " Noah Goldstein
2022-06-28 14:38 ` H.J. Lu
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