From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 0D4E13858D1E for ; Tue, 3 Jan 2023 21:15:58 +0000 (GMT) Received: by mail-ej1-x632.google.com with SMTP id t17so77155609eju.1 for ; Tue, 03 Jan 2023 13:15:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=1i0WgPBA1UPW+6QjMCntsnDmmW+dTLDCq0V1zYezGg0=; b=K8P6OZTWtC3muvcN+FjIFl9Q7PZFxBLssjoyVfNmdqE2yssvZJQOA+BPmAVuDIwJWK OCbxKCWFYQg2G0DbyikRCR/ePyNXVGQDt9aEd80/a6Gu6qg69R5fEbM7IjAXXPY7eqqI 7NXzrvWwmDYipuMxh/UcWgGigGdmsW3lhYsEEnOjW9eJp5F2YV2RXDGXocPmmgEgq1Yx 5AK2Cmqd6X0TjSl6jQ6ZLZRLpUSVQugmh/mCQ1iZJ7P7p8Evc2D4B1z+oyFjHtRZImkO DFORY8nxcYSZvPPYo+wCLc1JktwNsrPFCaUTDF2wJ9C6SiwTnBo7lkGoE3XdjLc/C9yz gn2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1i0WgPBA1UPW+6QjMCntsnDmmW+dTLDCq0V1zYezGg0=; b=MBzU8KYRgZIa+F0eE/73ZNjkZi0VoBaWhi8trnHGE9ZBedCxBXRciFrYHFtiUyIR4D RkQwMTs9zq+y1RS3t/FTU9y9PUM5pJDirBKm15HsgcLZQURFYzlJm/L6TJn3lmI3tGul IMETUKpyofau5qZ4M/9EgNrngR6XS1xzMz2zGSF9G5YMDDcy4Q/SUb2f/uNiRWnRQxv3 WZzKDIgZjDdtCNUwsXdYbXloadUnuHd6MjRzL0aqLUX80i971CLIqyHLXWgAibDpX4gr f0w+x3eSKsVFTpEeWQAsbfTtu7kAWVabikCWqFF/tX+4c1IMObdhYWqOBksfnPzJD8X8 BW+w== X-Gm-Message-State: AFqh2krdZHdYlOcHn4K+bF4nnTHniHJuVxuAUO/zj+kPrqk6gpByPMru SyAR6tbZbCP3NGFt4SSL+D5Pc2DvOLdQxIbs/UBYuzDJ X-Google-Smtp-Source: AMrXdXv+/h1LdG/6cd+s1tjlh83qxUiUIisPKmRF2EmupfnJnaQfAZrt6AW0ZiCJthpiu/ckAvZbza3hL6Ccwxyy7Ds= X-Received: by 2002:a17:907:20a2:b0:79d:f5f2:6f55 with SMTP id pw2-20020a17090720a200b0079df5f26f55mr2426781ejb.531.1672780556442; Tue, 03 Jan 2023 13:15:56 -0800 (PST) MIME-Version: 1.0 References: <20230103210648.2569652-1-hjl.tools@gmail.com> In-Reply-To: <20230103210648.2569652-1-hjl.tools@gmail.com> From: Noah Goldstein Date: Tue, 3 Jan 2023 13:15:44 -0800 Message-ID: Subject: Re: [PATCH v2] x86: Check minimum/maximum of non_temporal_threshold [BZ #29953] To: "H.J. Lu" Cc: libc-alpha@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Jan 3, 2023 at 1:06 PM H.J. Lu wrote: > > The minimum non_temporal_threshold is 0x4040. non_temporal_threshold may > be set to less than the minimum value when the shared cache size isn't > available (e.g., in an emulator) or by the tunable. Add checks for > minimum and maximum of non_temporal_threshold. > > This fixes BZ #29953. > --- > sysdeps/x86/dl-cacheinfo.h | 25 ++++++++++++++++--------- > 1 file changed, 16 insertions(+), 9 deletions(-) > > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > index e9f3382108..637b5a022d 100644 > --- a/sysdeps/x86/dl-cacheinfo.h > +++ b/sysdeps/x86/dl-cacheinfo.h > @@ -861,6 +861,18 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > share of the cache, it has a substantial risk of negatively > impacting the performance of other threads running on the chip. */ > unsigned long int non_temporal_threshold = shared * 3 / 4; > + /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of > + 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best > + if that operation cannot overflow. Minimum of 0x4040 (16448) because the > + L(large_memset_4x) loops need 64-byte to cache align and enough space for > + at least 1 iteration of 4x PAGE_SIZE unrolled loop. Both values are > + reflected in the manual. */ > + unsigned long int maximum_non_temporal_threshold = SIZE_MAX >> 4; > + unsigned long int minimum_non_temporal_threshold = 0x4040; > + if (non_temporal_threshold < minimum_non_temporal_threshold) > + non_temporal_threshold = minimum_non_temporal_threshold; > + else if (non_temporal_threshold > maximum_non_temporal_threshold) > + non_temporal_threshold = maximum_non_temporal_threshold; > > #if HAVE_TUNABLES > /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */ > @@ -915,8 +927,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > shared = tunable_size; > > tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); > - /* NB: Ignore the default value 0. */ > - if (tunable_size != 0) > + if (tunable_size > minimum_non_temporal_threshold > + && tunable_size <= maximum_non_temporal_threshold) > non_temporal_threshold = tunable_size; > > tunable_size = TUNABLE_GET (x86_rep_movsb_threshold, long int, NULL); > @@ -931,14 +943,9 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > > TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, data, 0, SIZE_MAX); > TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, shared, 0, SIZE_MAX); > - /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of > - 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best > - if that operation cannot overflow. Minimum of 0x4040 (16448) because the > - L(large_memset_4x) loops need 64-byte to cache align and enough space for > - at least 1 iteration of 4x PAGE_SIZE unrolled loop. Both values are > - reflected in the manual. */ > TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, non_temporal_threshold, > - 0x4040, SIZE_MAX >> 4); > + minimum_non_temporal_threshold, > + maximum_non_temporal_threshold); > TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, rep_movsb_threshold, > minimum_rep_movsb_threshold, SIZE_MAX); > TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, rep_stosb_threshold, 1, > -- > 2.39.0 > LGTM.