* [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds
@ 2022-06-17 3:50 Noah Goldstein
2022-06-17 3:50 ` [PATCH v1 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
` (7 more replies)
0 siblings, 8 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-17 3:50 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86/isa-level.c | 17 +---
sysdeps/x86/isa-level.h | 70 +++++++++++++
sysdeps/x86_64/isa-default-include.h | 49 +++++++++
sysdeps/x86_64/multiarch/isa-ifunc-macros.h | 106 ++++++++++++++++++++
4 files changed, 230 insertions(+), 12 deletions(-)
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-include.h
create mode 100644 sysdeps/x86_64/multiarch/isa-ifunc-macros.h
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..8e899bf64b 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if __X86_ISA_V1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if __X86_ISA_V2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if __X86_ISA_V3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if __X86_ISA_V4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..ed696ae8eb
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,70 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2020-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+# if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+# else
+# define __X86_ISA_V1 0
+# endif
+
+# if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
+ && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
+ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+# else
+# define __X86_ISA_V2 0
+# endif
+
+# if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+# else
+# define __X86_ISA_V3 0
+# endif
+
+# if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ \
+ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+# else
+# define __X86_ISA_V4 0
+# endif
+
+#define __X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-include.h b/sysdeps/x86_64/isa-default-include.h
new file mode 100644
index 0000000000..d3091340af
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-include.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2021-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_V2
+# define DEFAULT_V2 DEFAULT_V1
+#endif
+
+#ifndef DEFAULT_V3
+# define DEFAULT_V3 DEFAULT_V2
+#endif
+
+#ifndef DEFAULT_V4
+# define DEFAULT_V4 DEFAULT_V3
+#endif
+
+#define IS_DEFAULT_INCLUDE
+
+#if __X86_ISA_LEVEL == 1
+# include DEFAULT_V1
+#elif __X86_ISA_LEVEL == 2
+# include DEFAULT_V2
+#elif __X86_ISA_LEVEL == 3
+# include DEFAULT_V3
+#elif __X86_ISA_LEVEL == 4
+# include DEFAULT_V4
+#else
+# error "Unsupport ISA Level!"
+#endif
diff --git a/sysdeps/x86_64/multiarch/isa-ifunc-macros.h b/sysdeps/x86_64/multiarch/isa-ifunc-macros.h
new file mode 100644
index 0000000000..c24f2ab655
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/isa-ifunc-macros.h
@@ -0,0 +1,106 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2017-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <init-arch.h>
+#include <isa-level.h>
+
+#define OPTIMIZE_DECL(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
+
+#define OPTIMIZE_DECL1(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
+
+/* Only include at the level of the build ISA or better. I.e if built
+ with ISA=V1, then include all implementations. On the other hand if
+ built with ISA=V3 only include V3/V4 implementations. If there is
+ not implementation at or above the build ISA level, then include
+ the highest ISA level implementation. */
+#if __X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
+# define DECLARE_X86_OPTIMIZE_V4(...) OPTIMIZE_DECL (__VA_ARGS__)
+# define DECLARE_X86_OPTIMIZE1_V4(...) OPTIMIZE_DECL1 (__VA_ARGS__)
+#endif
+#if __X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
+# define DECLARE_X86_OPTIMIZE_V3(...) OPTIMIZE_DECL (__VA_ARGS__)
+# define DECLARE_X86_OPTIMIZE1_V3(...) OPTIMIZE_DECL1 (__VA_ARGS__)
+#endif
+#if __X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
+# define DECLARE_X86_OPTIMIZE_V2(...) OPTIMIZE_DECL (__VA_ARGS__)
+# define DECLARE_X86_OPTIMIZE1_V2(...) OPTIMIZE_DECL1 (__VA_ARGS__)
+#endif
+#if __X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
+# define DECLARE_X86_OPTIMIZE_V1(...) OPTIMIZE_DECL (__VA_ARGS__)
+# define DECLARE_X86_OPTIMIZE1_V1(...) OPTIMIZE_DECL1 (__VA_ARGS__)
+#endif
+
+#ifndef return_X86_OPTIMIZE_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+# define return_X86_OPTIMIZE_V4(...) (void) (0)
+# define return_X86_OPTIMIZE1_V4(...) (void) (0)
+# define DECLARE_X86_OPTIMIZE_V4(...)
+# define DECLARE_X86_OPTIMIZE1_V4(...)
+#endif
+#ifndef return_X86_OPTIMIZE_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+# define return_X86_OPTIMIZE_V3(...) (void) (0)
+# define return_X86_OPTIMIZE1_V3(...) (void) (0)
+# define DECLARE_X86_OPTIMIZE_V3(...)
+# define DECLARE_X86_OPTIMIZE1_V3(...)
+#endif
+#ifndef return_X86_OPTIMIZE_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+# define return_X86_OPTIMIZE_V2(...) (void) (0)
+# define return_X86_OPTIMIZE1_V2(...) (void) (0)
+# define DECLARE_X86_OPTIMIZE_V2(...)
+# define DECLARE_X86_OPTIMIZE1_V2(...)
+#endif
+#ifndef return_X86_OPTIMIZE_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+# define return_X86_OPTIMIZE_V1(...) (void) (0)
+# define return_X86_OPTIMIZE1_V1(...) (void) (0)
+# define DECLARE_X86_OPTIMIZE_V1(...)
+# define DECLARE_X86_OPTIMIZE1_V1(...)
+#endif
+
+#define DECLARE_X86_OPTIMIZE_FORCE(...) OPTIMIZE_DECL (__VA_ARGS__)
+#define return_X86_OPTIMIZE_FORCE(...) return OPTIMIZE (__VA_ARGS__)
+#define X86_IFUNC_IMPL_ADD_FORCE(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+
+#if __X86_ISA_LEVEL == 1
+# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
+#elif __X86_ISA_LEVEL == 2
+# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
+#elif __X86_ISA_LEVEL == 3
+# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
+#elif __X86_ISA_LEVEL == 4
+# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
+#else
+# error "Unsupported ISA Level"
+#endif
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v1 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-17 3:50 ` Noah Goldstein
2022-06-17 19:13 ` [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
` (6 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-17 3:50 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 34 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 74 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
20 files changed, 776 insertions(+), 609 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..1f7a7a2551 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-include.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..ba583161e6 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -17,19 +17,25 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <init-arch.h>
+#include "isa-ifunc-macros.h"
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+DECLARE_X86_OPTIMIZE_V4 (evex);
+DECLARE_X86_OPTIMIZE_V4 (evex_rtm);
+DECLARE_X86_OPTIMIZE_V3 (avx2);
+DECLARE_X86_OPTIMIZE_V3 (avx2_rtm);
+/* Declare sse2 version (ISA V1) V2 so that V2 build will have a fallback.
+ If an ISA V2 implementation is added update the ISA level build
+ guard in the -sse.S file and ISA version in ifunc-impl-list.c. */
+DECLARE_X86_OPTIMIZE_V2 (sse2);
+
+/* TODO: Look into using the ISA build level to remove some/all of the feature
+ checks. */
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
+ const struct cpu_features *cpu_features = __get_cpu_features ();
if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
&& CPU_FEATURE_USABLE_P (cpu_features, BMI2)
@@ -39,17 +45,21 @@ IFUNC_SELECTOR (void)
&& CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (evex_rtm);
+ return_X86_OPTIMIZE_V4 (evex_rtm);
- return OPTIMIZE (evex);
+ return_X86_OPTIMIZE_V4 (evex);
}
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (avx2_rtm);
+ return_X86_OPTIMIZE_V3 (avx2_rtm);
if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
- return OPTIMIZE (avx2);
+ return_X86_OPTIMIZE_V3 (avx2);
}
- return OPTIMIZE (sse2);
+ /* We cannot return NULL so include a fallback. This will only be hit in
+ cases where some ARCH_P feature makes a fallback to the ISA level
+ implementation somewhat undesirable. */
+ return X86_OPTIMIZE_FALLBACK (sse2 /* V1 impl */, sse2 /* V2 impl */,
+ avx2 /* V3 impl */, evex /* V4 impl */);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..f9cd7839f0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -23,9 +23,12 @@
#include <sysdep.h>
#include "init-arch.h"
+#include "isa-ifunc-macros.h"
+
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +56,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +294,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +757,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..9064d15ba7 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
+#endif
+
+#if (__X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined IS_DEFAULT_INCLUDE
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..ad93064b46 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
+#endif
+
+#if (__X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined IS_DEFAULT_INCLUDE
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..3cbc963474 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (__X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined IS_DEFAULT_INCLUDE
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..e48dbd6816 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (__X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined IS_DEFAULT_INCLUDE
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..b7130b7545 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-include.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..cbce00cbb9
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-include.h"
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-17 3:50 ` [PATCH v1 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-17 19:13 ` H.J. Lu
2022-06-17 19:30 ` Noah Goldstein
2022-06-21 21:29 ` Noah Goldstein
` (5 subsequent siblings)
7 siblings, 1 reply; 27+ messages in thread
From: H.J. Lu @ 2022-06-17 19:13 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Thu, Jun 16, 2022 at 8:50 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/x86/isa-level.c | 17 +---
> sysdeps/x86/isa-level.h | 70 +++++++++++++
> sysdeps/x86_64/isa-default-include.h | 49 +++++++++
> sysdeps/x86_64/multiarch/isa-ifunc-macros.h | 106 ++++++++++++++++++++
> 4 files changed, 230 insertions(+), 12 deletions(-)
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-include.h
> create mode 100644 sysdeps/x86_64/multiarch/isa-ifunc-macros.h
>
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..8e899bf64b 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if __X86_ISA_V1
#if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if __X86_ISA_V2
#if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if __X86_ISA_V3
#if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if __X86_ISA_V4
#if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..ed696ae8eb
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,70 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2020-2022 Free Software Foundation, Inc.
Just 2022.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +# if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +# else
> +# define __X86_ISA_V1 0
> +# endif
> +
> +# if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> + && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> + && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +# else
> +# define __X86_ISA_V2 0
> +# endif
> +
> +# if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +# else
> +# define __X86_ISA_V3 0
> +# endif
> +
> +# if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ \
> + && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +# else
> +# define __X86_ISA_V4 0
> +# endif
> +
> +#define __X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
We have isa.h to define MINIMUM_ISA. I think this file should define
MINIMUM_X86_ISA_LEVEL.
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-include.h b/sysdeps/x86_64/isa-default-include.h
> new file mode 100644
> index 0000000000..d3091340af
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-include.h
isa-default-impl.h? since this header file includes the default implementation.
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
Include the default implementation based on the minimum ISA level.
> + Copyright (C) 2021-2022 Free Software Foundation, Inc.
Just 2022.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_V1
ISA_DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
Must have at least ISA V1 implementation
> +#endif
> +
> +#ifndef DEFAULT_V2
> +# define DEFAULT_V2 DEFAULT_V1
> +#endif
> +
> +#ifndef DEFAULT_V3
> +# define DEFAULT_V3 DEFAULT_V2
> +#endif
> +
> +#ifndef DEFAULT_V4
> +# define DEFAULT_V4 DEFAULT_V3
> +#endif
> +
> +#define IS_DEFAULT_INCLUDE
We can remove IS_DEFAULT_INCLUDE and
check ISA_DEFAULT_IMPL instead.
> +
> +#if __X86_ISA_LEVEL == 1
#if MINIMUM_X86_ISA_LEVEL == 1
> +# include DEFAULT_V1
# define ISA_DEFAULT_IMPL ISA_DEFAULT_IMPL_V1
> +#elif __X86_ISA_LEVEL == 2
> +# include DEFAULT_V2
> +#elif __X86_ISA_LEVEL == 3
> +# include DEFAULT_V3
> +#elif __X86_ISA_LEVEL == 4
> +# include DEFAULT_V4
# define ISA_DEFAULT_IMPL ISA_DEFAULT_IMPL_V4
> +#else
> +# error "Unsupport ISA Level!"
> +#endif
#include ISA_DEFAULT_IMPL
> diff --git a/sysdeps/x86_64/multiarch/isa-ifunc-macros.h b/sysdeps/x86_64/multiarch/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..c24f2ab655
> --- /dev/null
> +++ b/sysdeps/x86_64/multiarch/isa-ifunc-macros.h
> @@ -0,0 +1,106 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2017-2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <init-arch.h>
> +#include <isa-level.h>
> +
> +#define OPTIMIZE_DECL(...) \
> + extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
> +
> +#define OPTIMIZE_DECL1(...) \
> + extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
> +
> +/* Only include at the level of the build ISA or better. I.e if built
minimum build ISA level
> + with ISA=V1, then include all implementations. On the other hand if
> + built with ISA=V3 only include V3/V4 implementations. If there is
> + not implementation at or above the build ISA level, then include
no implementation at or above the minimum build ISA level.
> + the highest ISA level implementation. */
> +#if __X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> +# define DECLARE_X86_OPTIMIZE_V4(...) OPTIMIZE_DECL (__VA_ARGS__)
> +# define DECLARE_X86_OPTIMIZE1_V4(...) OPTIMIZE_DECL1 (__VA_ARGS__)
These macros should be added to <init-arch.h> instead. I don't
think DECLARE_X86_OPTIMIZE_VN is necessary since unused
declarations are OK.
> +#endif
> +#if __X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> +# define DECLARE_X86_OPTIMIZE_V3(...) OPTIMIZE_DECL (__VA_ARGS__)
> +# define DECLARE_X86_OPTIMIZE1_V3(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> +#endif
> +#if __X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> +# define DECLARE_X86_OPTIMIZE_V2(...) OPTIMIZE_DECL (__VA_ARGS__)
> +# define DECLARE_X86_OPTIMIZE1_V2(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> +#endif
> +#if __X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> +# define DECLARE_X86_OPTIMIZE_V1(...) OPTIMIZE_DECL (__VA_ARGS__)
> +# define DECLARE_X86_OPTIMIZE1_V1(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> +#endif
> +
> +#ifndef return_X86_OPTIMIZE_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> +# define DECLARE_X86_OPTIMIZE_V4(...)
> +# define DECLARE_X86_OPTIMIZE1_V4(...)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> +# define DECLARE_X86_OPTIMIZE_V3(...)
> +# define DECLARE_X86_OPTIMIZE1_V3(...)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> +# define DECLARE_X86_OPTIMIZE_V2(...)
> +# define DECLARE_X86_OPTIMIZE1_V2(...)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> +# define DECLARE_X86_OPTIMIZE_V1(...)
> +# define DECLARE_X86_OPTIMIZE1_V1(...)
> +#endif
> +
> +#define DECLARE_X86_OPTIMIZE_FORCE(...) OPTIMIZE_DECL (__VA_ARGS__)
> +#define return_X86_OPTIMIZE_FORCE(...) return OPTIMIZE (__VA_ARGS__)
> +#define X86_IFUNC_IMPL_ADD_FORCE(...) IFUNC_IMPL_ADD (__VA_ARGS__)
These are unused.
> +#if __X86_ISA_LEVEL == 1
> +# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
> +#elif __X86_ISA_LEVEL == 2
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
> +#elif __X86_ISA_LEVEL == 3
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
> +#elif __X86_ISA_LEVEL == 4
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
> +#else
> +# error "Unsupported ISA Level"
> +#endif
> --
> 2.34.1
We can avoid X86_OPTIMIZE_FALLBACK by
1. Check the minimum ISA level IFUNC selector.
2. Turn return_X86_OPTIMIZE_VN into __builtin_unreachable ()
when unused.
Another issue. With AVX available, IFUNC selector may
prefer SSE version when AVX_Fast_Unaligned_Load or
Prefer_No_VZEROUPPER isn't set. This happens for memmove.
We have the default implementation without IFUNC and the
best implementation with IFUNC. They may not be the
same.
--
H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 19:13 ` [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
@ 2022-06-17 19:30 ` Noah Goldstein
2022-06-17 20:13 ` Noah Goldstein
0 siblings, 1 reply; 27+ messages in thread
From: Noah Goldstein @ 2022-06-17 19:30 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Fri, Jun 17, 2022 at 12:13 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Thu, Jun 16, 2022 at 8:50 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Factor out some of the ISA level defines in isa-level.c to
> > standalone header isa-level.h
> >
> > 2. Add new headers with ISA level dependent macros for handling
> > ifuncs.
> >
> > Note, this file does not change any code.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > ---
> > sysdeps/x86/isa-level.c | 17 +---
> > sysdeps/x86/isa-level.h | 70 +++++++++++++
> > sysdeps/x86_64/isa-default-include.h | 49 +++++++++
> > sysdeps/x86_64/multiarch/isa-ifunc-macros.h | 106 ++++++++++++++++++++
> > 4 files changed, 230 insertions(+), 12 deletions(-)
> > create mode 100644 sysdeps/x86/isa-level.h
> > create mode 100644 sysdeps/x86_64/isa-default-include.h
> > create mode 100644 sysdeps/x86_64/multiarch/isa-ifunc-macros.h
> >
> > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > index 09cd72ab20..8e899bf64b 100644
> > --- a/sysdeps/x86/isa-level.c
> > +++ b/sysdeps/x86/isa-level.c
> > @@ -26,38 +26,31 @@
> > <https://www.gnu.org/licenses/>. */
> >
> > #include <elf.h>
> > -
> > +#include <sysdeps/x86/isa-level.h>
> > /* ELF program property for x86 ISA level. */
> > #ifdef INCLUDE_X86_ISA_LEVEL
> > -# if defined __SSE__ && defined __SSE2__
> > +# if __X86_ISA_V1
>
> #if MINIMUM_X86_ISA_LEVEL >= 1
>
> > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > # else
> > # define ISA_BASELINE 0
> > # endif
> >
> > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > - && defined __SSE4_2__
> > +# if __X86_ISA_V2
>
> #if MINIMUM_X86_ISA_LEVEL >= 2
>
> > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > # else
> > # define ISA_V2 0
> > # endif
> >
> > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > - && defined __BMI__ && defined __BMI2__
> > +# if __X86_ISA_V3
>
> #if MINIMUM_X86_ISA_LEVEL >= 3
>
> > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > # else
> > # define ISA_V3 0
> > # endif
> >
> > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > - && defined __AVX512VL__
> > +# if __X86_ISA_V4
>
> #if MINIMUM_X86_ISA_LEVEL >= 4
>
> > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > # else
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > new file mode 100644
> > index 0000000000..ed696ae8eb
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -0,0 +1,70 @@
> > +/* Header defining the minimum x86 ISA level
> > + Copyright (C) 2020-2022 Free Software Foundation, Inc.
>
> Just 2022.
>
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + In addition to the permissions in the GNU Lesser General Public
> > + License, the Free Software Foundation gives you unlimited
> > + permission to link the compiled version of this file with other
> > + programs, and to distribute those programs without any restriction
> > + coming from the use of this file. (The Lesser General Public
> > + License restrictions do apply in other respects; for example, they
> > + cover modification of the file, and distribution when not linked
> > + into another program.)
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_LEVEL_H
> > +#define _ISA_LEVEL_H
> > +
> > +# if defined __SSE__ && defined __SSE2__
> > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > +# define __X86_ISA_V1 1
> > +# else
> > +# define __X86_ISA_V1 0
> > +# endif
> > +
> > +# if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > + && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > + && defined __SSE4_2__
> > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > +# define __X86_ISA_V2 1
> > +# else
> > +# define __X86_ISA_V2 0
> > +# endif
> > +
> > +# if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > + && defined __BMI__ && defined __BMI2__
> > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > +# define __X86_ISA_V3 1
> > +# else
> > +# define __X86_ISA_V3 0
> > +# endif
> > +
> > +# if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > + && defined __AVX512CD__ && defined __AVX512DQ__ \
> > + && defined __AVX512VL__
> > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > +# define __X86_ISA_V4 1
> > +# else
> > +# define __X86_ISA_V4 0
> > +# endif
> > +
> > +#define __X86_ISA_LEVEL \
> > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > +
>
> We have isa.h to define MINIMUM_ISA. I think this file should define
> MINIMUM_X86_ISA_LEVEL.
>
> > +#endif
> > diff --git a/sysdeps/x86_64/isa-default-include.h b/sysdeps/x86_64/isa-default-include.h
> > new file mode 100644
> > index 0000000000..d3091340af
> > --- /dev/null
> > +++ b/sysdeps/x86_64/isa-default-include.h
>
> isa-default-impl.h? since this header file includes the default implementation.
>
> > @@ -0,0 +1,49 @@
> > +/* Utility for including proper default function based on ISA level
>
> Include the default implementation based on the minimum ISA level.
>
> > + Copyright (C) 2021-2022 Free Software Foundation, Inc.
>
> Just 2022.
>
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include <isa-level.h>
> > +
> > +#ifndef DEFAULT_V1
>
> ISA_DEFAULT_IMPL_V1
>
> > +# error "Must have at least ISA V1 Version"
>
> Must have at least ISA V1 implementation
>
> > +#endif
> > +
> > +#ifndef DEFAULT_V2
> > +# define DEFAULT_V2 DEFAULT_V1
> > +#endif
> > +
> > +#ifndef DEFAULT_V3
> > +# define DEFAULT_V3 DEFAULT_V2
> > +#endif
> > +
> > +#ifndef DEFAULT_V4
> > +# define DEFAULT_V4 DEFAULT_V3
> > +#endif
> > +
> > +#define IS_DEFAULT_INCLUDE
>
> We can remove IS_DEFAULT_INCLUDE and
> check ISA_DEFAULT_IMPL instead.
>
> > +
> > +#if __X86_ISA_LEVEL == 1
>
> #if MINIMUM_X86_ISA_LEVEL == 1
>
> > +# include DEFAULT_V1
>
> # define ISA_DEFAULT_IMPL ISA_DEFAULT_IMPL_V1
>
> > +#elif __X86_ISA_LEVEL == 2
> > +# include DEFAULT_V2
> > +#elif __X86_ISA_LEVEL == 3
> > +# include DEFAULT_V3
> > +#elif __X86_ISA_LEVEL == 4
> > +# include DEFAULT_V4
>
> # define ISA_DEFAULT_IMPL ISA_DEFAULT_IMPL_V4
>
> > +#else
> > +# error "Unsupport ISA Level!"
> > +#endif
>
> #include ISA_DEFAULT_IMPL
>
> > diff --git a/sysdeps/x86_64/multiarch/isa-ifunc-macros.h b/sysdeps/x86_64/multiarch/isa-ifunc-macros.h
> > new file mode 100644
> > index 0000000000..c24f2ab655
> > --- /dev/null
> > +++ b/sysdeps/x86_64/multiarch/isa-ifunc-macros.h
> > @@ -0,0 +1,106 @@
> > +/* Common ifunc selection utils
> > + All versions must be listed in ifunc-impl-list.c.
> > + Copyright (C) 2017-2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include <init-arch.h>
> > +#include <isa-level.h>
> > +
> > +#define OPTIMIZE_DECL(...) \
> > + extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
> > +
> > +#define OPTIMIZE_DECL1(...) \
> > + extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
> > +
> > +/* Only include at the level of the build ISA or better. I.e if built
>
> minimum build ISA level
>
> > + with ISA=V1, then include all implementations. On the other hand if
> > + built with ISA=V3 only include V3/V4 implementations. If there is
> > + not implementation at or above the build ISA level, then include
>
> no implementation at or above the minimum build ISA level.
>
> > + the highest ISA level implementation. */
> > +#if __X86_ISA_LEVEL <= 4
> > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> > +# define DECLARE_X86_OPTIMIZE_V4(...) OPTIMIZE_DECL (__VA_ARGS__)
> > +# define DECLARE_X86_OPTIMIZE1_V4(...) OPTIMIZE_DECL1 (__VA_ARGS__)
>
> These macros should be added to <init-arch.h> instead. I don't
> think DECLARE_X86_OPTIMIZE_VN is necessary since unused
> declarations are OK.
Its not unused declaration is declaration of function that doesn't
exist.
But if can remove will do so for V2.
>
> > +#endif
> > +#if __X86_ISA_LEVEL <= 3
> > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> > +# define DECLARE_X86_OPTIMIZE_V3(...) OPTIMIZE_DECL (__VA_ARGS__)
> > +# define DECLARE_X86_OPTIMIZE1_V3(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> > +#endif
> > +#if __X86_ISA_LEVEL <= 2
> > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> > +# define DECLARE_X86_OPTIMIZE_V2(...) OPTIMIZE_DECL (__VA_ARGS__)
> > +# define DECLARE_X86_OPTIMIZE1_V2(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> > +#endif
> > +#if __X86_ISA_LEVEL <= 1
> > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> > +# define DECLARE_X86_OPTIMIZE_V1(...) OPTIMIZE_DECL (__VA_ARGS__)
> > +# define DECLARE_X86_OPTIMIZE1_V1(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> > +#endif
> > +
> > +#ifndef return_X86_OPTIMIZE_V4
> > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> > +# define DECLARE_X86_OPTIMIZE_V4(...)
> > +# define DECLARE_X86_OPTIMIZE1_V4(...)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V3
> > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> > +# define DECLARE_X86_OPTIMIZE_V3(...)
> > +# define DECLARE_X86_OPTIMIZE1_V3(...)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V2
> > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> > +# define DECLARE_X86_OPTIMIZE_V2(...)
> > +# define DECLARE_X86_OPTIMIZE1_V2(...)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V1
> > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> > +# define DECLARE_X86_OPTIMIZE_V1(...)
> > +# define DECLARE_X86_OPTIMIZE1_V1(...)
> > +#endif
> > +
> > +#define DECLARE_X86_OPTIMIZE_FORCE(...) OPTIMIZE_DECL (__VA_ARGS__)
> > +#define return_X86_OPTIMIZE_FORCE(...) return OPTIMIZE (__VA_ARGS__)
> > +#define X86_IFUNC_IMPL_ADD_FORCE(...) IFUNC_IMPL_ADD (__VA_ARGS__)
>
> These are unused.
Think will be used for strcspn/strspn/strpbrk but can drop for now.
>
> > +#if __X86_ISA_LEVEL == 1
> > +# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
> > +#elif __X86_ISA_LEVEL == 2
> > +# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
> > +#elif __X86_ISA_LEVEL == 3
> > +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
> > +#elif __X86_ISA_LEVEL == 4
> > +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
> > +#else
> > +# error "Unsupported ISA Level"
> > +#endif
> > --
> > 2.34.1
>
> We can avoid X86_OPTIMIZE_FALLBACK by
>
> 1. Check the minimum ISA level IFUNC selector.
> 2. Turn return_X86_OPTIMIZE_VN into __builtin_unreachable ()
> when unused.
I think there are some edge cases we may miss. I.e an ISA v3 implementation
that also has prefer_novzeroupper. It is still correct to use avx2 impl with
vzeroupper but we will fail in the ifunc preference.
All other suggestions will fix for v2.
>
> Another issue. With AVX available, IFUNC selector may
> prefer SSE version when AVX_Fast_Unaligned_Load or
> Prefer_No_VZEROUPPER isn't set. This happens for memmove.
> We have the default implementation without IFUNC and the
> best implementation with IFUNC. They may not be the
> same.
>
> --
> H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 19:30 ` Noah Goldstein
@ 2022-06-17 20:13 ` Noah Goldstein
0 siblings, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-17 20:13 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Fri, Jun 17, 2022 at 12:30 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Fri, Jun 17, 2022 at 12:13 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Thu, Jun 16, 2022 at 8:50 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > 1. Factor out some of the ISA level defines in isa-level.c to
> > > standalone header isa-level.h
> > >
> > > 2. Add new headers with ISA level dependent macros for handling
> > > ifuncs.
> > >
> > > Note, this file does not change any code.
> > >
> > > Tested with and without multiarch on x86_64 for ISA levels:
> > > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > > ---
> > > sysdeps/x86/isa-level.c | 17 +---
> > > sysdeps/x86/isa-level.h | 70 +++++++++++++
> > > sysdeps/x86_64/isa-default-include.h | 49 +++++++++
> > > sysdeps/x86_64/multiarch/isa-ifunc-macros.h | 106 ++++++++++++++++++++
> > > 4 files changed, 230 insertions(+), 12 deletions(-)
> > > create mode 100644 sysdeps/x86/isa-level.h
> > > create mode 100644 sysdeps/x86_64/isa-default-include.h
> > > create mode 100644 sysdeps/x86_64/multiarch/isa-ifunc-macros.h
> > >
> > > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > > index 09cd72ab20..8e899bf64b 100644
> > > --- a/sysdeps/x86/isa-level.c
> > > +++ b/sysdeps/x86/isa-level.c
> > > @@ -26,38 +26,31 @@
> > > <https://www.gnu.org/licenses/>. */
> > >
> > > #include <elf.h>
> > > -
> > > +#include <sysdeps/x86/isa-level.h>
> > > /* ELF program property for x86 ISA level. */
> > > #ifdef INCLUDE_X86_ISA_LEVEL
> > > -# if defined __SSE__ && defined __SSE2__
> > > +# if __X86_ISA_V1
> >
> > #if MINIMUM_X86_ISA_LEVEL >= 1
> >
> > > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > > # else
> > > # define ISA_BASELINE 0
> > > # endif
> > >
> > > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > > - && defined __SSE4_2__
> > > +# if __X86_ISA_V2
> >
> > #if MINIMUM_X86_ISA_LEVEL >= 2
> >
> > > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > > # else
> > > # define ISA_V2 0
> > > # endif
> > >
> > > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > > - && defined __BMI__ && defined __BMI2__
> > > +# if __X86_ISA_V3
> >
> > #if MINIMUM_X86_ISA_LEVEL >= 3
> >
> > > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > > # else
> > > # define ISA_V3 0
> > > # endif
> > >
> > > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > > - && defined __AVX512VL__
> > > +# if __X86_ISA_V4
> >
> > #if MINIMUM_X86_ISA_LEVEL >= 4
> >
> > > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > > # else
> > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > new file mode 100644
> > > index 0000000000..ed696ae8eb
> > > --- /dev/null
> > > +++ b/sysdeps/x86/isa-level.h
> > > @@ -0,0 +1,70 @@
> > > +/* Header defining the minimum x86 ISA level
> > > + Copyright (C) 2020-2022 Free Software Foundation, Inc.
> >
> > Just 2022.
> >
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + In addition to the permissions in the GNU Lesser General Public
> > > + License, the Free Software Foundation gives you unlimited
> > > + permission to link the compiled version of this file with other
> > > + programs, and to distribute those programs without any restriction
> > > + coming from the use of this file. (The Lesser General Public
> > > + License restrictions do apply in other respects; for example, they
> > > + cover modification of the file, and distribution when not linked
> > > + into another program.)
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#ifndef _ISA_LEVEL_H
> > > +#define _ISA_LEVEL_H
> > > +
> > > +# if defined __SSE__ && defined __SSE2__
> > > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > > +# define __X86_ISA_V1 1
> > > +# else
> > > +# define __X86_ISA_V1 0
> > > +# endif
> > > +
> > > +# if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > > + && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > > + && defined __SSE4_2__
> > > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > > +# define __X86_ISA_V2 1
> > > +# else
> > > +# define __X86_ISA_V2 0
> > > +# endif
> > > +
> > > +# if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > > + && defined __BMI__ && defined __BMI2__
> > > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > > +# define __X86_ISA_V3 1
> > > +# else
> > > +# define __X86_ISA_V3 0
> > > +# endif
> > > +
> > > +# if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > > + && defined __AVX512CD__ && defined __AVX512DQ__ \
> > > + && defined __AVX512VL__
> > > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > > +# define __X86_ISA_V4 1
> > > +# else
> > > +# define __X86_ISA_V4 0
> > > +# endif
> > > +
> > > +#define __X86_ISA_LEVEL \
> > > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > > +
> >
> > We have isa.h to define MINIMUM_ISA. I think this file should define
> > MINIMUM_X86_ISA_LEVEL.
> >
> > > +#endif
> > > diff --git a/sysdeps/x86_64/isa-default-include.h b/sysdeps/x86_64/isa-default-include.h
> > > new file mode 100644
> > > index 0000000000..d3091340af
> > > --- /dev/null
> > > +++ b/sysdeps/x86_64/isa-default-include.h
> >
> > isa-default-impl.h? since this header file includes the default implementation.
> >
> > > @@ -0,0 +1,49 @@
> > > +/* Utility for including proper default function based on ISA level
> >
> > Include the default implementation based on the minimum ISA level.
> >
> > > + Copyright (C) 2021-2022 Free Software Foundation, Inc.
> >
> > Just 2022.
> >
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#include <isa-level.h>
> > > +
> > > +#ifndef DEFAULT_V1
> >
> > ISA_DEFAULT_IMPL_V1
> >
> > > +# error "Must have at least ISA V1 Version"
> >
> > Must have at least ISA V1 implementation
> >
> > > +#endif
> > > +
> > > +#ifndef DEFAULT_V2
> > > +# define DEFAULT_V2 DEFAULT_V1
> > > +#endif
> > > +
> > > +#ifndef DEFAULT_V3
> > > +# define DEFAULT_V3 DEFAULT_V2
> > > +#endif
> > > +
> > > +#ifndef DEFAULT_V4
> > > +# define DEFAULT_V4 DEFAULT_V3
> > > +#endif
> > > +
> > > +#define IS_DEFAULT_INCLUDE
> >
> > We can remove IS_DEFAULT_INCLUDE and
> > check ISA_DEFAULT_IMPL instead.
> >
> > > +
> > > +#if __X86_ISA_LEVEL == 1
> >
> > #if MINIMUM_X86_ISA_LEVEL == 1
> >
> > > +# include DEFAULT_V1
> >
> > # define ISA_DEFAULT_IMPL ISA_DEFAULT_IMPL_V1
> >
> > > +#elif __X86_ISA_LEVEL == 2
> > > +# include DEFAULT_V2
> > > +#elif __X86_ISA_LEVEL == 3
> > > +# include DEFAULT_V3
> > > +#elif __X86_ISA_LEVEL == 4
> > > +# include DEFAULT_V4
> >
> > # define ISA_DEFAULT_IMPL ISA_DEFAULT_IMPL_V4
> >
> > > +#else
> > > +# error "Unsupport ISA Level!"
> > > +#endif
> >
> > #include ISA_DEFAULT_IMPL
> >
> > > diff --git a/sysdeps/x86_64/multiarch/isa-ifunc-macros.h b/sysdeps/x86_64/multiarch/isa-ifunc-macros.h
> > > new file mode 100644
> > > index 0000000000..c24f2ab655
> > > --- /dev/null
> > > +++ b/sysdeps/x86_64/multiarch/isa-ifunc-macros.h
> > > @@ -0,0 +1,106 @@
> > > +/* Common ifunc selection utils
> > > + All versions must be listed in ifunc-impl-list.c.
> > > + Copyright (C) 2017-2022 Free Software Foundation, Inc.
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#include <init-arch.h>
> > > +#include <isa-level.h>
> > > +
> > > +#define OPTIMIZE_DECL(...) \
> > > + extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
> > > +
> > > +#define OPTIMIZE_DECL1(...) \
> > > + extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
> > > +
> > > +/* Only include at the level of the build ISA or better. I.e if built
> >
> > minimum build ISA level
> >
> > > + with ISA=V1, then include all implementations. On the other hand if
> > > + built with ISA=V3 only include V3/V4 implementations. If there is
> > > + not implementation at or above the build ISA level, then include
> >
> > no implementation at or above the minimum build ISA level.
> >
> > > + the highest ISA level implementation. */
> > > +#if __X86_ISA_LEVEL <= 4
> > > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> > > +# define DECLARE_X86_OPTIMIZE_V4(...) OPTIMIZE_DECL (__VA_ARGS__)
> > > +# define DECLARE_X86_OPTIMIZE1_V4(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> >
> > These macros should be added to <init-arch.h> instead. I don't
> > think DECLARE_X86_OPTIMIZE_VN is necessary since unused
> > declarations are OK.
>
> Its not unused declaration is declaration of function that doesn't
> exist.
>
> But if can remove will do so for V2.
> >
> > > +#endif
> > > +#if __X86_ISA_LEVEL <= 3
> > > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> > > +# define DECLARE_X86_OPTIMIZE_V3(...) OPTIMIZE_DECL (__VA_ARGS__)
> > > +# define DECLARE_X86_OPTIMIZE1_V3(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> > > +#endif
> > > +#if __X86_ISA_LEVEL <= 2
> > > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> > > +# define DECLARE_X86_OPTIMIZE_V2(...) OPTIMIZE_DECL (__VA_ARGS__)
> > > +# define DECLARE_X86_OPTIMIZE1_V2(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> > > +#endif
> > > +#if __X86_ISA_LEVEL <= 1
> > > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> > > +# define DECLARE_X86_OPTIMIZE_V1(...) OPTIMIZE_DECL (__VA_ARGS__)
> > > +# define DECLARE_X86_OPTIMIZE1_V1(...) OPTIMIZE_DECL1 (__VA_ARGS__)
> > > +#endif
> > > +
> > > +#ifndef return_X86_OPTIMIZE_V4
> > > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > > +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> > > +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> > > +# define DECLARE_X86_OPTIMIZE_V4(...)
> > > +# define DECLARE_X86_OPTIMIZE1_V4(...)
> > > +#endif
> > > +#ifndef return_X86_OPTIMIZE_V3
> > > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > > +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> > > +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> > > +# define DECLARE_X86_OPTIMIZE_V3(...)
> > > +# define DECLARE_X86_OPTIMIZE1_V3(...)
> > > +#endif
> > > +#ifndef return_X86_OPTIMIZE_V2
> > > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > > +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> > > +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> > > +# define DECLARE_X86_OPTIMIZE_V2(...)
> > > +# define DECLARE_X86_OPTIMIZE1_V2(...)
> > > +#endif
> > > +#ifndef return_X86_OPTIMIZE_V1
> > > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > > +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> > > +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> > > +# define DECLARE_X86_OPTIMIZE_V1(...)
> > > +# define DECLARE_X86_OPTIMIZE1_V1(...)
> > > +#endif
> > > +
> > > +#define DECLARE_X86_OPTIMIZE_FORCE(...) OPTIMIZE_DECL (__VA_ARGS__)
> > > +#define return_X86_OPTIMIZE_FORCE(...) return OPTIMIZE (__VA_ARGS__)
> > > +#define X86_IFUNC_IMPL_ADD_FORCE(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> >
> > These are unused.
>
> Think will be used for strcspn/strspn/strpbrk but can drop for now.
> >
> > > +#if __X86_ISA_LEVEL == 1
> > > +# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
> > > +#elif __X86_ISA_LEVEL == 2
> > > +# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
> > > +#elif __X86_ISA_LEVEL == 3
> > > +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
> > > +#elif __X86_ISA_LEVEL == 4
> > > +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
> > > +#else
> > > +# error "Unsupported ISA Level"
> > > +#endif
> > > --
> > > 2.34.1
> >
> > We can avoid X86_OPTIMIZE_FALLBACK by
> >
> > 1. Check the minimum ISA level IFUNC selector.
> > 2. Turn return_X86_OPTIMIZE_VN into __builtin_unreachable ()
> > when unused.
>
> I think there are some edge cases we may miss. I.e an ISA v3 implementation
> that also has prefer_novzeroupper. It is still correct to use avx2 impl with
> vzeroupper but we will fail in the ifunc preference.
>
> All other suggestions will fix for v2.
>
>
> >
> > Another issue. With AVX available, IFUNC selector may
> > prefer SSE version when AVX_Fast_Unaligned_Load or
> > Prefer_No_VZEROUPPER isn't set. This happens for memmove.
> > We have the default implementation without IFUNC and the
> > best implementation with IFUNC. They may not be the
> > same.
We won't have SSE built in that case. Think we are going to be forced
to just eat the AVX implementation in that case.
> >
> > --
> > H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-17 3:50 ` [PATCH v1 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-17 19:13 ` [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
@ 2022-06-21 21:29 ` Noah Goldstein
2022-06-21 21:29 ` [PATCH v1 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-21 21:44 ` [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
` (4 subsequent siblings)
7 siblings, 1 reply; 27+ messages in thread
From: Noah Goldstein @ 2022-06-21 21:29 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/generic/ifunc-init.h | 8 ++
sysdeps/x86/init-arch.h | 4 +
sysdeps/x86/isa-cpu-feature-checks.h | 55 +++++++++++++
sysdeps/x86/isa-ifunc-macros.h | 117 +++++++++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++--
sysdeps/x86/isa-level.h | 67 +++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++
7 files changed, 305 insertions(+), 12 deletions(-)
create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
index 929e22ff5d..76f91c663c 100644
--- a/sysdeps/generic/ifunc-init.h
+++ b/sysdeps/generic/ifunc-init.h
@@ -55,3 +55,11 @@
#define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
/* Default is to use OPTIMIZE2. */
#define OPTIMIZE(name) OPTIMIZE2(name)
+
+/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
+ respectively. */
+#define OPTIMIZE_DECL(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
+
+#define OPTIMIZE_DECL1(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..68e3ecf8c0 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -27,6 +27,10 @@
# define USE_I586 0
# define USE_I686 1
# else
+
+# include <isa-ifunc-macros.h>
+# include <isa-cpu-feature-checks.h>
+
# define USE_I586 (HAS_ARCH_FEATURE (I586) && !HAS_ARCH_FEATURE (I686))
# define USE_I686 HAS_ARCH_FEATURE (I686)
# endif
diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
new file mode 100644
index 0000000000..ee2a9bba75
--- /dev/null
+++ b/sysdeps/x86/isa-cpu-feature-checks.h
@@ -0,0 +1,55 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2017-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_CPU_FEATURE_CHECKS_H
+#define _ISA_CPU_FEATURE_CHECKS_H 1
+
+#include <isa-level.h>
+
+/* ISA level >= 4 guaranteed includes. */
+#define X86_FEATURE_USABLE_P_AVX512VL \
+ (MINIMUM_X86_ISA_LEVEL >= 4 || CPU_FEATURE_USABLE_P (cpu_features, AVX512VL))
+
+#define X86_FEATURE_USABLE_P_AVX512BW \
+ (MINIMUM_X86_ISA_LEVEL >= 4 || CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+
+/* ISA level >= 3 guaranteed includes. */
+#define X86_FEATURE_USABLE_P_AVX2 \
+ (MINIMUM_X86_ISA_LEVEL >= 3 || CPU_FEATURE_USABLE_P (cpu_features, AVX2))
+
+#define X86_FEATURE_USABLE_P_BMI2 \
+ (MINIMUM_X86_ISA_LEVEL >= 3 || CPU_FEATURE_USABLE_P (cpu_features, BMI2))
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From looking over
+ * the architectures supported in cpu-features.h the following CPUs may have an
+ * issue with this being default set:
+ * - AMD Excavator
+ */
+#define X86_FEATURE_ARCH_P_AVX_Fast_Unaligned_Load \
+ (MINIMUM_X86_ISA_LEVEL >= 3 \
+ || CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+
+/* ISA independent non-guaranteed includes. */
+#define X86_FEATURE_USABLE_P_RTM CPU_FEATURE_USABLE_P (cpu_features, RTM)
+
+#define X86_FEATURE_ARCH_P_Prefer_No_VZEROUPPER \
+ CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER)
+
+#endif
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..3844f9e31c
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,117 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2017-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+
+#ifndef return_X86_OPTIMIZE_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+# define return_X86_OPTIMIZE_V4(...) (void) (0)
+# define return_X86_OPTIMIZE1_V4(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+# define return_X86_OPTIMIZE_V3(...) (void) (0)
+# define return_X86_OPTIMIZE1_V3(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+# define return_X86_OPTIMIZE_V2(...) (void) (0)
+# define return_X86_OPTIMIZE1_V2(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+# define return_X86_OPTIMIZE_V1(...) (void) (0)
+# define return_X86_OPTIMIZE1_V1(...) (void) (0)
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
+#else
+# error "Unsupported ISA Level"
+#endif
+
+
+#if MINIMUM_X86_ISA_LEVEL >= 4
+__errordecl (__unreachable_isa_above_4,
+ "This code should be unreachable if ISA level >= 4 build ");
+# define X86_ERROR_IF_REACHABLE_V4() \
+ __unreachable_isa_above_4 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V4()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 3
+__errordecl (__unreachable_isa_above_3,
+ "This code should be unreachable if ISA level >= 3 build");
+# define X86_ERROR_IF_REACHABLE_V3() \
+ __unreachable_isa_above_3 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V3()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 2
+__errordecl (__unreachable_isa_above_2,
+ "This code should be unreachable if ISA level >= 2 build");
+# define X86_ERROR_IF_REACHABLE_V2() \
+ __unreachable_isa_above_2 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V2()
+#endif
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..33dec72bde
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,67 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..db0635c8e7
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupport ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v1 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-21 21:29 ` Noah Goldstein
@ 2022-06-21 21:29 ` Noah Goldstein
0 siblings, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-21 21:29 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 46 ++-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
20 files changed, 779 insertions(+), 616 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..018bb06f04 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..57b365a664 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,37 +19,45 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+OPTIMIZE_DECL (evex);
+OPTIMIZE_DECL (evex_rtm);
+OPTIMIZE_DECL (avx2);
+OPTIMIZE_DECL (avx2_rtm);
+OPTIMIZE_DECL (sse2);
+
+/* TODO: Look into using the ISA build level to remove some/all of the feature
+ checks. */
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
+ const struct cpu_features *cpu_features = __get_cpu_features ();
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ if (X86_FEATURE_USABLE_P_AVX2 && X86_FEATURE_USABLE_P_BMI2
+ && X86_FEATURE_ARCH_P_AVX_Fast_Unaligned_Load)
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_FEATURE_USABLE_P_AVX512VL && X86_FEATURE_USABLE_P_AVX512BW)
{
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (evex_rtm);
+ if (X86_FEATURE_USABLE_P_RTM)
+ return_X86_OPTIMIZE_V4 (evex_rtm);
- return OPTIMIZE (evex);
+ return_X86_OPTIMIZE_V4 (evex);
}
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (avx2_rtm);
+ X86_ERROR_IF_REACHABLE_V4 ();
+
+ if (X86_FEATURE_USABLE_P_RTM || !X86_FEATURE_ARCH_P_Prefer_No_VZEROUPPER)
+ return_X86_OPTIMIZE_V3 (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
- return OPTIMIZE (avx2);
+ return_X86_OPTIMIZE_V3 (avx2);
}
- return OPTIMIZE (sse2);
+ X86_ERROR_IF_REACHABLE_V3 ();
+
+ /* We cannot return NULL so include a fallback. This will only be hit in
+ cases where some ARCH_P feature makes a fallback to the ISA level
+ implementation somewhat undesirable. */
+ return X86_OPTIMIZE_FALLBACK (sse2 /* V1 impl */, sse2 /* V2 impl */,
+ avx2 /* V3 impl */, evex /* V4 impl */);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..eda711ce13 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..72ea54c5af 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..603cd3baa0 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..5141a4deac 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..e401a2ac53 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-impl.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..dd0490f86b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
` (2 preceding siblings ...)
2022-06-21 21:29 ` Noah Goldstein
@ 2022-06-21 21:44 ` Noah Goldstein
2022-06-21 21:44 ` [PATCH v3 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-21 21:56 ` [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 0:30 ` [PATCH v4 " Noah Goldstein
` (3 subsequent siblings)
7 siblings, 2 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-21 21:44 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/generic/ifunc-init.h | 8 ++
sysdeps/x86/init-arch.h | 5 +-
sysdeps/x86/isa-cpu-feature-checks.h | 55 +++++++++++++
sysdeps/x86/isa-ifunc-macros.h | 117 +++++++++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++--
sysdeps/x86/isa-level.h | 67 +++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++
7 files changed, 305 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
index 929e22ff5d..76f91c663c 100644
--- a/sysdeps/generic/ifunc-init.h
+++ b/sysdeps/generic/ifunc-init.h
@@ -55,3 +55,11 @@
#define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
/* Default is to use OPTIMIZE2. */
#define OPTIMIZE(name) OPTIMIZE2(name)
+
+/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
+ respectively. */
+#define OPTIMIZE_DECL(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
+
+#define OPTIMIZE_DECL1(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a9fb4a1975 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,10 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+# include <isa-cpu-feature-checks.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
new file mode 100644
index 0000000000..5900a04599
--- /dev/null
+++ b/sysdeps/x86/isa-cpu-feature-checks.h
@@ -0,0 +1,55 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_CPU_FEATURE_CHECKS_H
+#define _ISA_CPU_FEATURE_CHECKS_H 1
+
+#include <isa-level.h>
+
+/* ISA level >= 4 guaranteed includes. */
+#define X86_FEATURE_USABLE_P_AVX512VL \
+ (MINIMUM_X86_ISA_LEVEL >= 4 || CPU_FEATURE_USABLE_P (cpu_features, AVX512VL))
+
+#define X86_FEATURE_USABLE_P_AVX512BW \
+ (MINIMUM_X86_ISA_LEVEL >= 4 || CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+
+/* ISA level >= 3 guaranteed includes. */
+#define X86_FEATURE_USABLE_P_AVX2 \
+ (MINIMUM_X86_ISA_LEVEL >= 3 || CPU_FEATURE_USABLE_P (cpu_features, AVX2))
+
+#define X86_FEATURE_USABLE_P_BMI2 \
+ (MINIMUM_X86_ISA_LEVEL >= 3 || CPU_FEATURE_USABLE_P (cpu_features, BMI2))
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From looking over
+ * the architectures supported in cpu-features.h the following CPUs may have an
+ * issue with this being default set:
+ * - AMD Excavator
+ */
+#define X86_FEATURE_ARCH_P_AVX_Fast_Unaligned_Load \
+ (MINIMUM_X86_ISA_LEVEL >= 3 \
+ || CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+
+/* ISA independent non-guaranteed includes. */
+#define X86_FEATURE_USABLE_P_RTM CPU_FEATURE_USABLE_P (cpu_features, RTM)
+
+#define X86_FEATURE_ARCH_P_Prefer_No_VZEROUPPER \
+ CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER)
+
+#endif
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..69895e26ca
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,117 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+
+#ifndef return_X86_OPTIMIZE_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+# define return_X86_OPTIMIZE_V4(...) (void) (0)
+# define return_X86_OPTIMIZE1_V4(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+# define return_X86_OPTIMIZE_V3(...) (void) (0)
+# define return_X86_OPTIMIZE1_V3(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+# define return_X86_OPTIMIZE_V2(...) (void) (0)
+# define return_X86_OPTIMIZE1_V2(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+# define return_X86_OPTIMIZE_V1(...) (void) (0)
+# define return_X86_OPTIMIZE1_V1(...) (void) (0)
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
+#else
+# error "Unsupported ISA Level"
+#endif
+
+
+#if MINIMUM_X86_ISA_LEVEL >= 4
+__errordecl (__unreachable_isa_above_4,
+ "This code should be unreachable if ISA level >= 4 build ");
+# define X86_ERROR_IF_REACHABLE_V4() \
+ __unreachable_isa_above_4 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V4()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 3
+__errordecl (__unreachable_isa_above_3,
+ "This code should be unreachable if ISA level >= 3 build");
+# define X86_ERROR_IF_REACHABLE_V3() \
+ __unreachable_isa_above_3 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V3()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 2
+__errordecl (__unreachable_isa_above_2,
+ "This code should be unreachable if ISA level >= 2 build");
+# define X86_ERROR_IF_REACHABLE_V2() \
+ __unreachable_isa_above_2 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V2()
+#endif
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..33dec72bde
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,67 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..db0635c8e7
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupport ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-21 21:44 ` [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-21 21:44 ` Noah Goldstein
2022-06-21 21:56 ` [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
1 sibling, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-21 21:44 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 46 ++-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
20 files changed, 779 insertions(+), 616 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..018bb06f04 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..57b365a664 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,37 +19,45 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+OPTIMIZE_DECL (evex);
+OPTIMIZE_DECL (evex_rtm);
+OPTIMIZE_DECL (avx2);
+OPTIMIZE_DECL (avx2_rtm);
+OPTIMIZE_DECL (sse2);
+
+/* TODO: Look into using the ISA build level to remove some/all of the feature
+ checks. */
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
+ const struct cpu_features *cpu_features = __get_cpu_features ();
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ if (X86_FEATURE_USABLE_P_AVX2 && X86_FEATURE_USABLE_P_BMI2
+ && X86_FEATURE_ARCH_P_AVX_Fast_Unaligned_Load)
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_FEATURE_USABLE_P_AVX512VL && X86_FEATURE_USABLE_P_AVX512BW)
{
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (evex_rtm);
+ if (X86_FEATURE_USABLE_P_RTM)
+ return_X86_OPTIMIZE_V4 (evex_rtm);
- return OPTIMIZE (evex);
+ return_X86_OPTIMIZE_V4 (evex);
}
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (avx2_rtm);
+ X86_ERROR_IF_REACHABLE_V4 ();
+
+ if (X86_FEATURE_USABLE_P_RTM || !X86_FEATURE_ARCH_P_Prefer_No_VZEROUPPER)
+ return_X86_OPTIMIZE_V3 (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
- return OPTIMIZE (avx2);
+ return_X86_OPTIMIZE_V3 (avx2);
}
- return OPTIMIZE (sse2);
+ X86_ERROR_IF_REACHABLE_V3 ();
+
+ /* We cannot return NULL so include a fallback. This will only be hit in
+ cases where some ARCH_P feature makes a fallback to the ISA level
+ implementation somewhat undesirable. */
+ return X86_OPTIMIZE_FALLBACK (sse2 /* V1 impl */, sse2 /* V2 impl */,
+ avx2 /* V3 impl */, evex /* V4 impl */);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..eda711ce13 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..72ea54c5af 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..603cd3baa0 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..5141a4deac 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined IS_DEFAULT_INCLUDE
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..e401a2ac53 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-impl.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..dd0490f86b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-21 21:44 ` [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-21 21:44 ` [PATCH v3 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-21 21:56 ` H.J. Lu
1 sibling, 0 replies; 27+ messages in thread
From: H.J. Lu @ 2022-06-21 21:56 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Tue, Jun 21, 2022 at 2:44 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/generic/ifunc-init.h | 8 ++
> sysdeps/x86/init-arch.h | 5 +-
> sysdeps/x86/isa-cpu-feature-checks.h | 55 +++++++++++++
> sysdeps/x86/isa-ifunc-macros.h | 117 +++++++++++++++++++++++++++
> sysdeps/x86/isa-level.c | 17 ++--
> sysdeps/x86/isa-level.h | 67 +++++++++++++++
> sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++
> 7 files changed, 305 insertions(+), 13 deletions(-)
> create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
> create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-impl.h
>
> diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
> index 929e22ff5d..76f91c663c 100644
> --- a/sysdeps/generic/ifunc-init.h
> +++ b/sysdeps/generic/ifunc-init.h
> @@ -55,3 +55,11 @@
> #define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
> /* Default is to use OPTIMIZE2. */
> #define OPTIMIZE(name) OPTIMIZE2(name)
> +
> +/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
> + respectively. */
> +#define OPTIMIZE_DECL(...) \
> + extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
> +
> +#define OPTIMIZE_DECL1(...) \
> + extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
> diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> index 277c15f116..a9fb4a1975 100644
> --- a/sysdeps/x86/init-arch.h
> +++ b/sysdeps/x86/init-arch.h
> @@ -19,7 +19,10 @@
> #include <ifunc-init.h>
> #include <isa.h>
>
> -#ifndef __x86_64__
> +#ifdef __x86_64__
> +# include <isa-ifunc-macros.h>
> +# include <isa-cpu-feature-checks.h>
> +#else
> /* Due to the reordering and the other nifty extensions in i686, it is
> not really good to use heavily i586 optimized code on an i686. It's
> better to use i486 code if it isn't an i586. */
> diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
> new file mode 100644
> index 0000000000..5900a04599
> --- /dev/null
> +++ b/sysdeps/x86/isa-cpu-feature-checks.h
> @@ -0,0 +1,55 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_CPU_FEATURE_CHECKS_H
> +#define _ISA_CPU_FEATURE_CHECKS_H 1
> +
> +#include <isa-level.h>
> +
> +/* ISA level >= 4 guaranteed includes. */
> +#define X86_FEATURE_USABLE_P_AVX512VL \
> + (MINIMUM_X86_ISA_LEVEL >= 4 || CPU_FEATURE_USABLE_P (cpu_features, AVX512VL))
>
cpu_features should be an argument. How about
#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
(name ## _X86_ISA_LEVEL <= MINIMUM_X86_ISA_LEVEL \
|| CPU_FEATURE_USABLE_P (ptr, name)
Also please limit lines to 72 columns.
> +#define X86_FEATURE_USABLE_P_AVX512BW \
> + (MINIMUM_X86_ISA_LEVEL >= 4 || CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
> +
> +/* ISA level >= 3 guaranteed includes. */
> +#define X86_FEATURE_USABLE_P_AVX2 \
> + (MINIMUM_X86_ISA_LEVEL >= 3 || CPU_FEATURE_USABLE_P (cpu_features, AVX2))
> +
> +#define X86_FEATURE_USABLE_P_BMI2 \
> + (MINIMUM_X86_ISA_LEVEL >= 3 || CPU_FEATURE_USABLE_P (cpu_features, BMI2))
> +
> +/*
> + * NB: This may not be fully assumable for ISA level >= 3. From looking over
> + * the architectures supported in cpu-features.h the following CPUs may have an
> + * issue with this being default set:
> + * - AMD Excavator
> + */
> +#define X86_FEATURE_ARCH_P_AVX_Fast_Unaligned_Load \
> + (MINIMUM_X86_ISA_LEVEL >= 3 \
> + || CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
> +
> +/* ISA independent non-guaranteed includes. */
> +#define X86_FEATURE_USABLE_P_RTM CPU_FEATURE_USABLE_P (cpu_features, RTM)
> +
> +#define X86_FEATURE_ARCH_P_Prefer_No_VZEROUPPER \
> + CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER)
> +
> +#endif
> diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..69895e26ca
> --- /dev/null
> +++ b/sysdeps/x86/isa-ifunc-macros.h
> @@ -0,0 +1,117 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_IFUNC_MACROS_H
> +#define _ISA_IFUNC_MACROS_H 1
> +
> +#include <isa-level.h>
> +#include <sys/cdefs.h>
> +
> +/* Only include at the level of the minimum build ISA or higher. I.e
> + if built with ISA=V1, then include all implementations. On the
> + other hand if built with ISA=V3 only include V3/V4
> + implementations. If there is no implementation at or above the
> + minimum build ISA level, then include the highest ISA level
> + implementation. */
> +#if MINIMUM_X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +
> +#ifndef return_X86_OPTIMIZE_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
> +#else
> +# error "Unsupported ISA Level"
> +#endif
> +
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 4
> +__errordecl (__unreachable_isa_above_4,
> + "This code should be unreachable if ISA level >= 4 build ");
> +# define X86_ERROR_IF_REACHABLE_V4() \
> + __unreachable_isa_above_4 (); \
> + __builtin_unreachable ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V4()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 3
> +__errordecl (__unreachable_isa_above_3,
> + "This code should be unreachable if ISA level >= 3 build");
> +# define X86_ERROR_IF_REACHABLE_V3() \
> + __unreachable_isa_above_3 (); \
> + __builtin_unreachable ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V3()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 2
> +__errordecl (__unreachable_isa_above_2,
> + "This code should be unreachable if ISA level >= 2 build");
> +# define X86_ERROR_IF_REACHABLE_V2() \
> + __unreachable_isa_above_2 (); \
> + __builtin_unreachable ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V2()
> +#endif
> +
> +#endif
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..5b7a2da870 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..33dec72bde
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,67 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +#if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +#else
> +# define __X86_ISA_V1 0
> +#endif
> +
> +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +#else
> +# define __X86_ISA_V2 0
> +#endif
> +
> +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +#else
> +# define __X86_ISA_V3 0
> +#endif
> +
> +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +#else
> +# define __X86_ISA_V4 0
> +#endif
> +
> +#define MINIMUM_X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> new file mode 100644
> index 0000000000..db0635c8e7
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V2
> +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V3
> +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V4
> +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> +#else
> +# error "Unsupport ISA Level!"
> +#endif
> +
> +#include ISA_DEFAULT_IMPL
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v4 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
` (3 preceding siblings ...)
2022-06-21 21:44 ` [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 0:30 ` Noah Goldstein
2022-06-22 0:30 ` [PATCH v4 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 1:36 ` [PATCH v4 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 2:05 ` [PATCH v5 " Noah Goldstein
` (2 subsequent siblings)
7 siblings, 2 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 0:30 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/generic/ifunc-init.h | 8 ++
sysdeps/x86/init-arch.h | 5 +-
sysdeps/x86/isa-cpu-feature-checks.h | 60 +++++++++++++
sysdeps/x86/isa-ifunc-macros.h | 130 +++++++++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++--
sysdeps/x86/isa-level.h | 67 ++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++
7 files changed, 323 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
index 929e22ff5d..76f91c663c 100644
--- a/sysdeps/generic/ifunc-init.h
+++ b/sysdeps/generic/ifunc-init.h
@@ -55,3 +55,11 @@
#define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
/* Default is to use OPTIMIZE2. */
#define OPTIMIZE(name) OPTIMIZE2(name)
+
+/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
+ respectively. */
+#define OPTIMIZE_DECL(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
+
+#define OPTIMIZE_DECL1(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a9fb4a1975 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,10 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+# include <isa-cpu-feature-checks.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
new file mode 100644
index 0000000000..44b77a8c1f
--- /dev/null
+++ b/sysdeps/x86/isa-cpu-feature-checks.h
@@ -0,0 +1,60 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_CPU_FEATURE_CHECKS_H
+#define _ISA_CPU_FEATURE_CHECKS_H 1
+
+/*
+ * CPU Features that are hard coded enabled / disabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+#include <isa-level.h>
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+/*
+ * ISA independent non-guaranteed includes. Set value at 255 which is
+ * greater than any forseable ISA level.
+ */
+#define RTM_X86_ISA_LEVEL 255
+
+#endif
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..4c28a057c5
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,130 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+
+#ifndef return_X86_OPTIMIZE_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+# define return_X86_OPTIMIZE_V4(...) (void) (0)
+# define return_X86_OPTIMIZE1_V4(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+# define return_X86_OPTIMIZE_V3(...) (void) (0)
+# define return_X86_OPTIMIZE1_V3(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+# define return_X86_OPTIMIZE_V2(...) (void) (0)
+# define return_X86_OPTIMIZE1_V2(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+# define return_X86_OPTIMIZE_V1(...) (void) (0)
+# define return_X86_OPTIMIZE1_V1(...) (void) (0)
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
+#else
+# error "Unsupported ISA Level"
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 4
+__errordecl (
+ __unreachable_isa_above_4,
+ "This code should be unreachable if ISA level >= 4 build ");
+# define X86_ERROR_IF_REACHABLE_V4() \
+ __unreachable_isa_above_4 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V4()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 3
+__errordecl (__unreachable_isa_above_3,
+ "This code should be unreachable if ISA level >= 3 build");
+# define X86_ERROR_IF_REACHABLE_V3() \
+ __unreachable_isa_above_3 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V3()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 2
+__errordecl (__unreachable_isa_above_2,
+ "This code should be unreachable if ISA level >= 2 build");
+# define X86_ERROR_IF_REACHABLE_V2() \
+ __unreachable_isa_above_2 (); \
+ __builtin_unreachable ();
+#else
+# define X86_ERROR_IF_REACHABLE_V2()
+#endif
+
+#define X86_ISA_CPU_FEATURE_NAME(name) (name##_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ (X86_ISA_CPU_FEATURE_NAME (name) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..33dec72bde
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,67 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..db0635c8e7
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupport ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v4 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 0:30 ` [PATCH v4 " Noah Goldstein
@ 2022-06-22 0:30 ` Noah Goldstein
2022-06-22 1:36 ` [PATCH v4 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
1 sibling, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 0:30 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/generic/ifunc-init.h | 8 -
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 45 ++-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
21 files changed, 780 insertions(+), 622 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
index 76f91c663c..929e22ff5d 100644
--- a/sysdeps/generic/ifunc-init.h
+++ b/sysdeps/generic/ifunc-init.h
@@ -55,11 +55,3 @@
#define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
/* Default is to use OPTIMIZE2. */
#define OPTIMIZE(name) OPTIMIZE2(name)
-
-/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
- respectively. */
-#define OPTIMIZE_DECL(...) \
- extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
-
-#define OPTIMIZE_DECL1(...) \
- extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..018bb06f04 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..3ad69eaee3 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,37 +19,48 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
+
+/* TODO: Look into using the ISA build level to remove some/all of the
+ feature checks. */
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
+ const struct cpu_features *cpu_features = __get_cpu_features ();
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (evex_rtm);
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, RTM))
+ return_X86_OPTIMIZE_V4 (evex_rtm);
- return OPTIMIZE (evex);
+ return_X86_OPTIMIZE_V4 (evex);
}
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (avx2_rtm);
+ X86_ERROR_IF_REACHABLE_V4 ();
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
- return OPTIMIZE (avx2);
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, RTM))
+ return_X86_OPTIMIZE_V3 (avx2_rtm);
+
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
+ return_X86_OPTIMIZE_V3 (avx2);
}
- return OPTIMIZE (sse2);
+ X86_ERROR_IF_REACHABLE_V3 ();
+
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
+ return_X86_OPTIMIZE_V2 (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..691662f0fb 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..10ed0434ae 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..acd5c15e22 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..73f4fa9589 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..e401a2ac53 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-impl.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..dd0490f86b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v4 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 0:30 ` [PATCH v4 " Noah Goldstein
2022-06-22 0:30 ` [PATCH v4 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 1:36 ` H.J. Lu
2022-06-22 2:05 ` Noah Goldstein
1 sibling, 1 reply; 27+ messages in thread
From: H.J. Lu @ 2022-06-22 1:36 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Tue, Jun 21, 2022 at 5:30 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/generic/ifunc-init.h | 8 ++
> sysdeps/x86/init-arch.h | 5 +-
> sysdeps/x86/isa-cpu-feature-checks.h | 60 +++++++++++++
> sysdeps/x86/isa-ifunc-macros.h | 130 +++++++++++++++++++++++++++
> sysdeps/x86/isa-level.c | 17 ++--
> sysdeps/x86/isa-level.h | 67 ++++++++++++++
> sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++
> 7 files changed, 323 insertions(+), 13 deletions(-)
> create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
> create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-impl.h
>
> diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
> index 929e22ff5d..76f91c663c 100644
> --- a/sysdeps/generic/ifunc-init.h
> +++ b/sysdeps/generic/ifunc-init.h
> @@ -55,3 +55,11 @@
> #define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
> /* Default is to use OPTIMIZE2. */
> #define OPTIMIZE(name) OPTIMIZE2(name)
> +
> +/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
> + respectively. */
> +#define OPTIMIZE_DECL(...) \
> + extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
> +
> +#define OPTIMIZE_DECL1(...) \
> + extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
Unrelated. Please remove them.
> diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> index 277c15f116..a9fb4a1975 100644
> --- a/sysdeps/x86/init-arch.h
> +++ b/sysdeps/x86/init-arch.h
> @@ -19,7 +19,10 @@
> #include <ifunc-init.h>
> #include <isa.h>
>
> -#ifndef __x86_64__
> +#ifdef __x86_64__
> +# include <isa-ifunc-macros.h>
> +# include <isa-cpu-feature-checks.h>
Why add 2 header files? Does one work?
> +#else
> /* Due to the reordering and the other nifty extensions in i686, it is
> not really good to use heavily i586 optimized code on an i686. It's
> better to use i486 code if it isn't an i586. */
> diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
> new file mode 100644
> index 0000000000..44b77a8c1f
> --- /dev/null
> +++ b/sysdeps/x86/isa-cpu-feature-checks.h
> @@ -0,0 +1,60 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_CPU_FEATURE_CHECKS_H
> +#define _ISA_CPU_FEATURE_CHECKS_H 1
> +
> +/*
> + * CPU Features that are hard coded enabled / disabled depending on ISA build
Do we disable an ISA feature? We check if a CPU Feature
is included for a given ISA level.
> + * level.
> + * - Values > 0 features are always ENABLED if:
> + * Value >= MINIMUM_X86_ISA_LEVEL
> + */
> +
> +#include <isa-level.h>
> +
> +/* ISA level >= 4 guaranteed includes. */
> +#define AVX512VL_X86_ISA_LEVEL 4
> +#define AVX512BW_X86_ISA_LEVEL 4
> +
> +/* ISA level >= 3 guaranteed includes. */
> +#define AVX2_X86_ISA_LEVEL 3
> +#define BMI2_X86_ISA_LEVEL 3
> +
> +/*
> + * NB: This may not be fully assumable for ISA level >= 3. From
> + * looking over the architectures supported in cpu-features.h the
> + * following CPUs may have an issue with this being default set:
> + * - AMD Excavator
> + */
> +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> +
> +/*
> + * KNL (the only cpu that sets this supported in cpu-features.h)
> + * builds with ISA V1 so this shouldn't harm any architectures.
> + */
> +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> +
> +/*
> + * ISA independent non-guaranteed includes. Set value at 255 which is
> + * greater than any forseable ISA level.
> + */
> +#define RTM_X86_ISA_LEVEL 255
Do we really need to define the ISA level for RTM?
> +
> +#endif
> diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..4c28a057c5
> --- /dev/null
> +++ b/sysdeps/x86/isa-ifunc-macros.h
> @@ -0,0 +1,130 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_IFUNC_MACROS_H
> +#define _ISA_IFUNC_MACROS_H 1
> +
> +#include <isa-level.h>
> +#include <sys/cdefs.h>
> +
> +/* Only include at the level of the minimum build ISA or higher. I.e
> + if built with ISA=V1, then include all implementations. On the
> + other hand if built with ISA=V3 only include V3/V4
> + implementations. If there is no implementation at or above the
> + minimum build ISA level, then include the highest ISA level
> + implementation. */
> +#if MINIMUM_X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +
> +#ifndef return_X86_OPTIMIZE_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
Do we need these? Shouldn't X86_ERROR_IF_REACHABLE be
sufficient?
> +#else
> +# error "Unsupported ISA Level"
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 4
> +__errordecl (
> + __unreachable_isa_above_4,
> + "This code should be unreachable if ISA level >= 4 build ");
> +# define X86_ERROR_IF_REACHABLE_V4() \
> + __unreachable_isa_above_4 (); \
> + __builtin_unreachable ();
Do we need __builtin_unreachable here? Compiler must
know it is unreachable.
> +#else
> +# define X86_ERROR_IF_REACHABLE_V4()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 3
> +__errordecl (__unreachable_isa_above_3,
> + "This code should be unreachable if ISA level >= 3 build");
> +# define X86_ERROR_IF_REACHABLE_V3() \
> + __unreachable_isa_above_3 (); \
> + __builtin_unreachable ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V3()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 2
> +__errordecl (__unreachable_isa_above_2,
> + "This code should be unreachable if ISA level >= 2 build");
> +# define X86_ERROR_IF_REACHABLE_V2() \
> + __unreachable_isa_above_2 (); \
> + __builtin_unreachable ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V2()
> +#endif
> +
> +#define X86_ISA_CPU_FEATURE_NAME(name) (name##_X86_ISA_LEVEL)
No need for this. This macro name is confusing.
> +
> +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> + (X86_ISA_CPU_FEATURE_NAME (name) <= MINIMUM_X86_ISA_LEVEL)
X86_ISA_CPU_FEATURE_INCLUDED?
> +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURE_USABLE_P (ptr, name))
> +
> +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURES_ARCH_P (ptr, name))
> +
> +#endif
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..5b7a2da870 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..33dec72bde
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,67 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +#if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +#else
> +# define __X86_ISA_V1 0
> +#endif
> +
> +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +#else
> +# define __X86_ISA_V2 0
> +#endif
> +
> +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +#else
> +# define __X86_ISA_V3 0
> +#endif
> +
> +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +#else
> +# define __X86_ISA_V4 0
> +#endif
> +
> +#define MINIMUM_X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> new file mode 100644
> index 0000000000..db0635c8e7
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V2
> +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V3
> +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V4
> +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> +#else
> +# error "Unsupport ISA Level!"
> +#endif
> +
> +#include ISA_DEFAULT_IMPL
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v5 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
` (4 preceding siblings ...)
2022-06-22 0:30 ` [PATCH v4 " Noah Goldstein
@ 2022-06-22 2:05 ` Noah Goldstein
2022-06-22 2:05 ` [PATCH v5 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 2:08 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 4:47 ` [PATCH v7 " Noah Goldstein
7 siblings, 1 reply; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 2:05 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/generic/ifunc-init.h | 8 ++
sysdeps/x86/init-arch.h | 5 +-
sysdeps/x86/isa-cpu-feature-checks.h | 60 ++++++++++++++
sysdeps/x86/isa-ifunc-macros.h | 113 +++++++++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++--
sysdeps/x86/isa-level.h | 67 ++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++
7 files changed, 306 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
index 929e22ff5d..76f91c663c 100644
--- a/sysdeps/generic/ifunc-init.h
+++ b/sysdeps/generic/ifunc-init.h
@@ -55,3 +55,11 @@
#define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
/* Default is to use OPTIMIZE2. */
#define OPTIMIZE(name) OPTIMIZE2(name)
+
+/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
+ respectively. */
+#define OPTIMIZE_DECL(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
+
+#define OPTIMIZE_DECL1(...) \
+ extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a9fb4a1975 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,10 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+# include <isa-cpu-feature-checks.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
new file mode 100644
index 0000000000..1bc02ab5b5
--- /dev/null
+++ b/sysdeps/x86/isa-cpu-feature-checks.h
@@ -0,0 +1,60 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_CPU_FEATURE_CHECKS_H
+#define _ISA_CPU_FEATURE_CHECKS_H 1
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+#include <isa-level.h>
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+/*
+ * ISA independent non-guaranteed includes. Set value at 255 which is
+ * greater than any foreseeable ISA level.
+ */
+#define RTM_X86_ISA_LEVEL 255
+
+#endif
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..1d1cd99e74
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,113 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+
+#ifndef return_X86_OPTIMIZE_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+# define return_X86_OPTIMIZE_V4(...) (void) (0)
+# define return_X86_OPTIMIZE1_V4(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+# define return_X86_OPTIMIZE_V3(...) (void) (0)
+# define return_X86_OPTIMIZE1_V3(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+# define return_X86_OPTIMIZE_V2(...) (void) (0)
+# define return_X86_OPTIMIZE1_V2(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+# define return_X86_OPTIMIZE_V1(...) (void) (0)
+# define return_X86_OPTIMIZE1_V1(...) (void) (0)
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 4
+__errordecl (
+ __unreachable_isa_above_4,
+ "This code should be unreachable if ISA level >= 4 build ");
+# define X86_ERROR_IF_REACHABLE_V4() \
+ __unreachable_isa_above_4 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V4()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 3
+__errordecl (__unreachable_isa_above_3,
+ "This code should be unreachable if ISA level >= 3 build");
+# define X86_ERROR_IF_REACHABLE_V3() \
+ __unreachable_isa_above_3 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V3()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 2
+__errordecl (__unreachable_isa_above_2,
+ "This code should be unreachable if ISA level >= 2 build");
+# define X86_ERROR_IF_REACHABLE_V2() \
+ __unreachable_isa_above_2 ();#else
+# define X86_ERROR_IF_REACHABLE_V2()
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..33dec72bde
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,67 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..db0635c8e7
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupport ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v5 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 2:05 ` [PATCH v5 " Noah Goldstein
@ 2022-06-22 2:05 ` Noah Goldstein
0 siblings, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 2:05 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/generic/ifunc-init.h | 8 -
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 45 ++-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
21 files changed, 780 insertions(+), 622 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
index 76f91c663c..929e22ff5d 100644
--- a/sysdeps/generic/ifunc-init.h
+++ b/sysdeps/generic/ifunc-init.h
@@ -55,11 +55,3 @@
#define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
/* Default is to use OPTIMIZE2. */
#define OPTIMIZE(name) OPTIMIZE2(name)
-
-/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
- respectively. */
-#define OPTIMIZE_DECL(...) \
- extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
-
-#define OPTIMIZE_DECL1(...) \
- extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..018bb06f04 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..3ad69eaee3 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,37 +19,48 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
+
+/* TODO: Look into using the ISA build level to remove some/all of the
+ feature checks. */
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
+ const struct cpu_features *cpu_features = __get_cpu_features ();
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (evex_rtm);
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, RTM))
+ return_X86_OPTIMIZE_V4 (evex_rtm);
- return OPTIMIZE (evex);
+ return_X86_OPTIMIZE_V4 (evex);
}
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (avx2_rtm);
+ X86_ERROR_IF_REACHABLE_V4 ();
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
- return OPTIMIZE (avx2);
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, RTM))
+ return_X86_OPTIMIZE_V3 (avx2_rtm);
+
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
+ return_X86_OPTIMIZE_V3 (avx2);
}
- return OPTIMIZE (sse2);
+ X86_ERROR_IF_REACHABLE_V3 ();
+
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
+ return_X86_OPTIMIZE_V2 (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..691662f0fb 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..10ed0434ae 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..acd5c15e22 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..73f4fa9589 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..e401a2ac53 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-impl.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..dd0490f86b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v4 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 1:36 ` [PATCH v4 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
@ 2022-06-22 2:05 ` Noah Goldstein
0 siblings, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 2:05 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Tue, Jun 21, 2022 at 6:37 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Tue, Jun 21, 2022 at 5:30 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Factor out some of the ISA level defines in isa-level.c to
> > standalone header isa-level.h
> >
> > 2. Add new headers with ISA level dependent macros for handling
> > ifuncs.
> >
> > Note, this file does not change any code.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > ---
> > sysdeps/generic/ifunc-init.h | 8 ++
> > sysdeps/x86/init-arch.h | 5 +-
> > sysdeps/x86/isa-cpu-feature-checks.h | 60 +++++++++++++
> > sysdeps/x86/isa-ifunc-macros.h | 130 +++++++++++++++++++++++++++
> > sysdeps/x86/isa-level.c | 17 ++--
> > sysdeps/x86/isa-level.h | 67 ++++++++++++++
> > sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++
> > 7 files changed, 323 insertions(+), 13 deletions(-)
> > create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
> > create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> > create mode 100644 sysdeps/x86/isa-level.h
> > create mode 100644 sysdeps/x86_64/isa-default-impl.h
> >
> > diff --git a/sysdeps/generic/ifunc-init.h b/sysdeps/generic/ifunc-init.h
> > index 929e22ff5d..76f91c663c 100644
> > --- a/sysdeps/generic/ifunc-init.h
> > +++ b/sysdeps/generic/ifunc-init.h
> > @@ -55,3 +55,11 @@
> > #define OPTIMIZE2(name) EVALUATOR2 (SYMBOL_NAME, name)
> > /* Default is to use OPTIMIZE2. */
> > #define OPTIMIZE(name) OPTIMIZE2(name)
> > +
> > +/* Syntactic sugar for common usage of the OPTIMIZE and OPTIMIZE1 macros
> > + respectively. */
> > +#define OPTIMIZE_DECL(...) \
> > + extern __typeof (REDIRECT_NAME) OPTIMIZE (__VA_ARGS__) attribute_hidden;
> > +
> > +#define OPTIMIZE_DECL1(...) \
> > + extern __typeof (REDIRECT_NAME) OPTIMIZE1 (__VA_ARGS__) attribute_hidden;
>
> Unrelated. Please remove them.
Sorry remove from ifunc, for here. Will do for V5.
>
> > diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> > index 277c15f116..a9fb4a1975 100644
> > --- a/sysdeps/x86/init-arch.h
> > +++ b/sysdeps/x86/init-arch.h
> > @@ -19,7 +19,10 @@
> > #include <ifunc-init.h>
> > #include <isa.h>
> >
> > -#ifndef __x86_64__
> > +#ifdef __x86_64__
> > +# include <isa-ifunc-macros.h>
> > +# include <isa-cpu-feature-checks.h>
>
> Why add 2 header files? Does one work?
They seem to be meaningfully distinct in what they do.
>
> > +#else
> > /* Due to the reordering and the other nifty extensions in i686, it is
> > not really good to use heavily i586 optimized code on an i686. It's
> > better to use i486 code if it isn't an i586. */
> > diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
> > new file mode 100644
> > index 0000000000..44b77a8c1f
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-cpu-feature-checks.h
> > @@ -0,0 +1,60 @@
> > +/* Common ifunc selection utils
> > + All versions must be listed in ifunc-impl-list.c.
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_CPU_FEATURE_CHECKS_H
> > +#define _ISA_CPU_FEATURE_CHECKS_H 1
> > +
> > +/*
> > + * CPU Features that are hard coded enabled / disabled depending on ISA build
>
> Do we disable an ISA feature? We check if a CPU Feature
> is included for a given ISA level.
it's just wording. Enabling means to ignore if a feature bit IS NOT set and
disabling ignoring if a feature bit IS set.
I.e skipping ARCH_P(Prefer_No_Vzeroupper) -> disabling a potentially set bit
skipping USABLE_P(AVX2) -> enabling a potentially not set bit.
Removed in v5 either way.
>
> > + * level.
> > + * - Values > 0 features are always ENABLED if:
> > + * Value >= MINIMUM_X86_ISA_LEVEL
> > + */
> > +
> > +#include <isa-level.h>
> > +
> > +/* ISA level >= 4 guaranteed includes. */
> > +#define AVX512VL_X86_ISA_LEVEL 4
> > +#define AVX512BW_X86_ISA_LEVEL 4
> > +
> > +/* ISA level >= 3 guaranteed includes. */
> > +#define AVX2_X86_ISA_LEVEL 3
> > +#define BMI2_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * NB: This may not be fully assumable for ISA level >= 3. From
> > + * looking over the architectures supported in cpu-features.h the
> > + * following CPUs may have an issue with this being default set:
> > + * - AMD Excavator
> > + */
> > +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * KNL (the only cpu that sets this supported in cpu-features.h)
> > + * builds with ISA V1 so this shouldn't harm any architectures.
> > + */
> > +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * ISA independent non-guaranteed includes. Set value at 255 which is
> > + * greater than any forseable ISA level.
> > + */
> > +#define RTM_X86_ISA_LEVEL 255
>
> Do we really need to define the ISA level for RTM?
Its just so we can consistently use the X86_ISA_CPU_FEATURE_... macros
in the ifunc selector.
>
> > +
> > +#endif
> > diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> > new file mode 100644
> > index 0000000000..4c28a057c5
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-ifunc-macros.h
> > @@ -0,0 +1,130 @@
> > +/* Common ifunc selection utils
> > + All versions must be listed in ifunc-impl-list.c.
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_IFUNC_MACROS_H
> > +#define _ISA_IFUNC_MACROS_H 1
> > +
> > +#include <isa-level.h>
> > +#include <sys/cdefs.h>
> > +
> > +/* Only include at the level of the minimum build ISA or higher. I.e
> > + if built with ISA=V1, then include all implementations. On the
> > + other hand if built with ISA=V3 only include V3/V4
> > + implementations. If there is no implementation at or above the
> > + minimum build ISA level, then include the highest ISA level
> > + implementation. */
> > +#if MINIMUM_X86_ISA_LEVEL <= 4
> > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 3
> > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 2
> > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 1
> > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +
> > +#ifndef return_X86_OPTIMIZE_V4
> > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V3
> > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V2
> > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V1
> > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL == 1
> > +# define X86_OPTIMIZE_FALLBACK(v1, ...) OPTIMIZE (v1)
> > +#elif MINIMUM_X86_ISA_LEVEL == 2
> > +# define X86_OPTIMIZE_FALLBACK(v1, v2, ...) OPTIMIZE (v2)
> > +#elif MINIMUM_X86_ISA_LEVEL == 3
> > +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, ...) OPTIMIZE (v3)
> > +#elif MINIMUM_X86_ISA_LEVEL == 4
> > +# define X86_OPTIMIZE_FALLBACK(v1, v2, v3, v4) OPTIMIZE (v4)
>
> Do we need these? Shouldn't X86_ERROR_IF_REACHABLE be
> sufficient?
Ah those are unused now. Will drop in V5.
>
> > +#else
> > +# error "Unsupported ISA Level"
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 4
> > +__errordecl (
> > + __unreachable_isa_above_4,
> > + "This code should be unreachable if ISA level >= 4 build ");
> > +# define X86_ERROR_IF_REACHABLE_V4() \
> > + __unreachable_isa_above_4 (); \
> > + __builtin_unreachable ();
>
> Do we need __builtin_unreachable here? Compiler must
> know it is unreachable.
Fair enough.
What do you think about putting abort() there just in case?
>
> > +#else
> > +# define X86_ERROR_IF_REACHABLE_V4()
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 3
> > +__errordecl (__unreachable_isa_above_3,
> > + "This code should be unreachable if ISA level >= 3 build");
> > +# define X86_ERROR_IF_REACHABLE_V3() \
> > + __unreachable_isa_above_3 (); \
> > + __builtin_unreachable ();
> > +#else
> > +# define X86_ERROR_IF_REACHABLE_V3()
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 2
> > +__errordecl (__unreachable_isa_above_2,
> > + "This code should be unreachable if ISA level >= 2 build");
> > +# define X86_ERROR_IF_REACHABLE_V2() \
> > + __unreachable_isa_above_2 (); \
> > + __builtin_unreachable ();
> > +#else
> > +# define X86_ERROR_IF_REACHABLE_V2()
> > +#endif
> > +
> > +#define X86_ISA_CPU_FEATURE_NAME(name) (name##_X86_ISA_LEVEL)
>
> No need for this. This macro name is confusing.
>
Dropped in V5.
> > +
> > +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> > + (X86_ISA_CPU_FEATURE_NAME (name) <= MINIMUM_X86_ISA_LEVEL)
>
> X86_ISA_CPU_FEATURE_INCLUDED?
>
> > +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > + || CPU_FEATURE_USABLE_P (ptr, name))
> > +
> > +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > + || CPU_FEATURES_ARCH_P (ptr, name))
> > +
> > +#endif
> > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > index 09cd72ab20..5b7a2da870 100644
> > --- a/sysdeps/x86/isa-level.c
> > +++ b/sysdeps/x86/isa-level.c
> > @@ -26,38 +26,31 @@
> > <https://www.gnu.org/licenses/>. */
> >
> > #include <elf.h>
> > -
> > +#include <sysdeps/x86/isa-level.h>
> > /* ELF program property for x86 ISA level. */
> > #ifdef INCLUDE_X86_ISA_LEVEL
> > -# if defined __SSE__ && defined __SSE2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 1
> > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > # else
> > # define ISA_BASELINE 0
> > # endif
> >
> > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > - && defined __SSE4_2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 2
> > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > # else
> > # define ISA_V2 0
> > # endif
> >
> > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > - && defined __BMI__ && defined __BMI2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 3
> > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > # else
> > # define ISA_V3 0
> > # endif
> >
> > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > - && defined __AVX512VL__
> > +# if MINIMUM_X86_ISA_LEVEL >= 4
> > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > # else
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > new file mode 100644
> > index 0000000000..33dec72bde
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -0,0 +1,67 @@
> > +/* Header defining the minimum x86 ISA level
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + In addition to the permissions in the GNU Lesser General Public
> > + License, the Free Software Foundation gives you unlimited
> > + permission to link the compiled version of this file with other
> > + programs, and to distribute those programs without any restriction
> > + coming from the use of this file. (The Lesser General Public
> > + License restrictions do apply in other respects; for example, they
> > + cover modification of the file, and distribution when not linked
> > + into another program.)
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_LEVEL_H
> > +#define _ISA_LEVEL_H
> > +
> > +#if defined __SSE__ && defined __SSE2__
> > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > +# define __X86_ISA_V1 1
> > +#else
> > +# define __X86_ISA_V1 0
> > +#endif
> > +
> > +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> > + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > +# define __X86_ISA_V2 1
> > +#else
> > +# define __X86_ISA_V2 0
> > +#endif
> > +
> > +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > + && defined __BMI__ && defined __BMI2__
> > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > +# define __X86_ISA_V3 1
> > +#else
> > +# define __X86_ISA_V3 0
> > +#endif
> > +
> > +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > +# define __X86_ISA_V4 1
> > +#else
> > +# define __X86_ISA_V4 0
> > +#endif
> > +
> > +#define MINIMUM_X86_ISA_LEVEL \
> > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > +
> > +#endif
> > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > new file mode 100644
> > index 0000000000..db0635c8e7
> > --- /dev/null
> > +++ b/sysdeps/x86_64/isa-default-impl.h
> > @@ -0,0 +1,49 @@
> > +/* Utility for including proper default function based on ISA level
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include <isa-level.h>
> > +
> > +#ifndef DEFAULT_IMPL_V1
> > +# error "Must have at least ISA V1 Version"
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V2
> > +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V3
> > +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V4
> > +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL == 1
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> > +#elif MINIMUM_X86_ISA_LEVEL == 2
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> > +#elif MINIMUM_X86_ISA_LEVEL == 3
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> > +#elif MINIMUM_X86_ISA_LEVEL == 4
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> > +#else
> > +# error "Unsupport ISA Level!"
> > +#endif
> > +
> > +#include ISA_DEFAULT_IMPL
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
` (5 preceding siblings ...)
2022-06-22 2:05 ` [PATCH v5 " Noah Goldstein
@ 2022-06-22 2:08 ` Noah Goldstein
2022-06-22 2:08 ` [PATCH v6 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 2:49 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 4:47 ` [PATCH v7 " Noah Goldstein
7 siblings, 2 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 2:08 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86/init-arch.h | 5 +-
sysdeps/x86/isa-cpu-feature-checks.h | 60 ++++++++++++++
sysdeps/x86/isa-ifunc-macros.h | 113 +++++++++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++--
sysdeps/x86/isa-level.h | 67 ++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++
6 files changed, 298 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a9fb4a1975 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,10 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+# include <isa-cpu-feature-checks.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
new file mode 100644
index 0000000000..1bc02ab5b5
--- /dev/null
+++ b/sysdeps/x86/isa-cpu-feature-checks.h
@@ -0,0 +1,60 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_CPU_FEATURE_CHECKS_H
+#define _ISA_CPU_FEATURE_CHECKS_H 1
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+#include <isa-level.h>
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+/*
+ * ISA independent non-guaranteed includes. Set value at 255 which is
+ * greater than any foreseeable ISA level.
+ */
+#define RTM_X86_ISA_LEVEL 255
+
+#endif
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..1d1cd99e74
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,113 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+
+#ifndef return_X86_OPTIMIZE_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+# define return_X86_OPTIMIZE_V4(...) (void) (0)
+# define return_X86_OPTIMIZE1_V4(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+# define return_X86_OPTIMIZE_V3(...) (void) (0)
+# define return_X86_OPTIMIZE1_V3(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+# define return_X86_OPTIMIZE_V2(...) (void) (0)
+# define return_X86_OPTIMIZE1_V2(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+# define return_X86_OPTIMIZE_V1(...) (void) (0)
+# define return_X86_OPTIMIZE1_V1(...) (void) (0)
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 4
+__errordecl (
+ __unreachable_isa_above_4,
+ "This code should be unreachable if ISA level >= 4 build ");
+# define X86_ERROR_IF_REACHABLE_V4() \
+ __unreachable_isa_above_4 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V4()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 3
+__errordecl (__unreachable_isa_above_3,
+ "This code should be unreachable if ISA level >= 3 build");
+# define X86_ERROR_IF_REACHABLE_V3() \
+ __unreachable_isa_above_3 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V3()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 2
+__errordecl (__unreachable_isa_above_2,
+ "This code should be unreachable if ISA level >= 2 build");
+# define X86_ERROR_IF_REACHABLE_V2() \
+ __unreachable_isa_above_2 ();#else
+# define X86_ERROR_IF_REACHABLE_V2()
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..33dec72bde
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,67 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..db0635c8e7
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupport ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v6 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 2:08 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 2:08 ` Noah Goldstein
2022-06-22 2:49 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
1 sibling, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 2:08 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 45 ++-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
20 files changed, 780 insertions(+), 614 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..018bb06f04 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..3ad69eaee3 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,37 +19,48 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
+
+/* TODO: Look into using the ISA build level to remove some/all of the
+ feature checks. */
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
+ const struct cpu_features *cpu_features = __get_cpu_features ();
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (evex_rtm);
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, RTM))
+ return_X86_OPTIMIZE_V4 (evex_rtm);
- return OPTIMIZE (evex);
+ return_X86_OPTIMIZE_V4 (evex);
}
- if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (avx2_rtm);
+ X86_ERROR_IF_REACHABLE_V4 ();
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
- return OPTIMIZE (avx2);
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, RTM))
+ return_X86_OPTIMIZE_V3 (avx2_rtm);
+
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
+ return_X86_OPTIMIZE_V3 (avx2);
}
- return OPTIMIZE (sse2);
+ X86_ERROR_IF_REACHABLE_V3 ();
+
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
+ return_X86_OPTIMIZE_V2 (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..691662f0fb 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..10ed0434ae 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..acd5c15e22 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..73f4fa9589 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..e401a2ac53 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-impl.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..dd0490f86b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 2:08 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 2:08 ` [PATCH v6 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 2:49 ` H.J. Lu
2022-06-22 4:47 ` Noah Goldstein
1 sibling, 1 reply; 27+ messages in thread
From: H.J. Lu @ 2022-06-22 2:49 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Tue, Jun 21, 2022 at 7:08 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/x86/init-arch.h | 5 +-
> sysdeps/x86/isa-cpu-feature-checks.h | 60 ++++++++++++++
> sysdeps/x86/isa-ifunc-macros.h | 113 +++++++++++++++++++++++++++
> sysdeps/x86/isa-level.c | 17 ++--
> sysdeps/x86/isa-level.h | 67 ++++++++++++++++
> sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++
> 6 files changed, 298 insertions(+), 13 deletions(-)
> create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
> create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-impl.h
>
> diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> index 277c15f116..a9fb4a1975 100644
> --- a/sysdeps/x86/init-arch.h
> +++ b/sysdeps/x86/init-arch.h
> @@ -19,7 +19,10 @@
> #include <ifunc-init.h>
> #include <isa.h>
>
> -#ifndef __x86_64__
> +#ifdef __x86_64__
> +# include <isa-ifunc-macros.h>
> +# include <isa-cpu-feature-checks.h>
> +#else
> /* Due to the reordering and the other nifty extensions in i686, it is
> not really good to use heavily i586 optimized code on an i686. It's
> better to use i486 code if it isn't an i586. */
> diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
> new file mode 100644
> index 0000000000..1bc02ab5b5
> --- /dev/null
> +++ b/sysdeps/x86/isa-cpu-feature-checks.h
> @@ -0,0 +1,60 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_CPU_FEATURE_CHECKS_H
> +#define _ISA_CPU_FEATURE_CHECKS_H 1
> +
> +/*
> + * CPU Features that are hard coded as enabled depending on ISA build
> + * level.
> + * - Values > 0 features are always ENABLED if:
> + * Value >= MINIMUM_X86_ISA_LEVEL
> + */
> +
> +#include <isa-level.h>
> +
> +/* ISA level >= 4 guaranteed includes. */
> +#define AVX512VL_X86_ISA_LEVEL 4
> +#define AVX512BW_X86_ISA_LEVEL 4
> +
> +/* ISA level >= 3 guaranteed includes. */
> +#define AVX2_X86_ISA_LEVEL 3
> +#define BMI2_X86_ISA_LEVEL 3
> +
> +/*
> + * NB: This may not be fully assumable for ISA level >= 3. From
> + * looking over the architectures supported in cpu-features.h the
> + * following CPUs may have an issue with this being default set:
> + * - AMD Excavator
> + */
> +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> +
> +/*
> + * KNL (the only cpu that sets this supported in cpu-features.h)
> + * builds with ISA V1 so this shouldn't harm any architectures.
> + */
> +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> +
> +/*
> + * ISA independent non-guaranteed includes. Set value at 255 which is
> + * greater than any foreseeable ISA level.
> + */
> +#define RTM_X86_ISA_LEVEL 255
No need for this. We shouldn't blindly change CPU_FEATURE_USABLE_P.
These macros belong to isa-level.h.
> +#endif
> diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..1d1cd99e74
> --- /dev/null
> +++ b/sysdeps/x86/isa-ifunc-macros.h
> @@ -0,0 +1,113 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_IFUNC_MACROS_H
> +#define _ISA_IFUNC_MACROS_H 1
> +
> +#include <isa-level.h>
> +#include <sys/cdefs.h>
> +#include <stdlib.h>
> +
> +/* Only include at the level of the minimum build ISA or higher. I.e
> + if built with ISA=V1, then include all implementations. On the
> + other hand if built with ISA=V3 only include V3/V4
> + implementations. If there is no implementation at or above the
> + minimum build ISA level, then include the highest ISA level
> + implementation. */
> +#if MINIMUM_X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +
> +#ifndef return_X86_OPTIMIZE_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 4
> +__errordecl (
> + __unreachable_isa_above_4,
> + "This code should be unreachable if ISA level >= 4 build ");
> +# define X86_ERROR_IF_REACHABLE_V4() \
> + __unreachable_isa_above_4 ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V4()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 3
> +__errordecl (__unreachable_isa_above_3,
> + "This code should be unreachable if ISA level >= 3 build");
> +# define X86_ERROR_IF_REACHABLE_V3() \
> + __unreachable_isa_above_3 ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V3()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 2
> +__errordecl (__unreachable_isa_above_2,
> + "This code should be unreachable if ISA level >= 2 build");
> +# define X86_ERROR_IF_REACHABLE_V2() \
> + __unreachable_isa_above_2 ();#else
^^^ Wrong place
> +# define X86_ERROR_IF_REACHABLE_V2()
> +#endif
> +
> +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> +
> +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURE_USABLE_P (ptr, name))
> +
> +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURES_ARCH_P (ptr, name))
> +
> +#endif
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..5b7a2da870 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..33dec72bde
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,67 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +#if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +#else
> +# define __X86_ISA_V1 0
> +#endif
> +
> +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +#else
> +# define __X86_ISA_V2 0
> +#endif
> +
> +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +#else
> +# define __X86_ISA_V3 0
> +#endif
> +
> +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +#else
> +# define __X86_ISA_V4 0
> +#endif
> +
> +#define MINIMUM_X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> new file mode 100644
> index 0000000000..db0635c8e7
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V2
> +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V3
> +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V4
> +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> +#else
> +# error "Unsupport ISA Level!"
> +#endif
> +
> +#include ISA_DEFAULT_IMPL
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
` (6 preceding siblings ...)
2022-06-22 2:08 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
@ 2022-06-22 4:47 ` Noah Goldstein
2022-06-22 4:47 ` [PATCH v7 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 14:19 ` [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
7 siblings, 2 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 4:47 UTC (permalink / raw)
To: libc-alpha
1. Factor out some of the ISA level defines in isa-level.c to
standalone header isa-level.h
2. Add new headers with ISA level dependent macros for handling
ifuncs.
Note, this file does not change any code.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86/init-arch.h | 4 +-
sysdeps/x86/isa-ifunc-macros.h | 111 ++++++++++++++++++++++++++++++
sysdeps/x86/isa-level.c | 17 ++---
sysdeps/x86/isa-level.h | 99 ++++++++++++++++++++++++++
sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++
5 files changed, 267 insertions(+), 13 deletions(-)
create mode 100644 sysdeps/x86/isa-ifunc-macros.h
create mode 100644 sysdeps/x86/isa-level.h
create mode 100644 sysdeps/x86_64/isa-default-impl.h
diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
index 277c15f116..a2886a2532 100644
--- a/sysdeps/x86/init-arch.h
+++ b/sysdeps/x86/init-arch.h
@@ -19,7 +19,9 @@
#include <ifunc-init.h>
#include <isa.h>
-#ifndef __x86_64__
+#ifdef __x86_64__
+# include <isa-ifunc-macros.h>
+#else
/* Due to the reordering and the other nifty extensions in i686, it is
not really good to use heavily i586 optimized code on an i686. It's
better to use i486 code if it isn't an i586. */
diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
new file mode 100644
index 0000000000..2aa8fab000
--- /dev/null
+++ b/sysdeps/x86/isa-ifunc-macros.h
@@ -0,0 +1,111 @@
+/* Common ifunc selection utils
+ All versions must be listed in ifunc-impl-list.c.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_IFUNC_MACROS_H
+#define _ISA_IFUNC_MACROS_H 1
+
+#include <isa-level.h>
+#include <sys/cdefs.h>
+#include <stdlib.h>
+
+/* Only include at the level of the minimum build ISA or higher. I.e
+ if built with ISA=V1, then include all implementations. On the
+ other hand if built with ISA=V3 only include V3/V4
+ implementations. If there is no implementation at or above the
+ minimum build ISA level, then include the highest ISA level
+ implementation. */
+#if MINIMUM_X86_ISA_LEVEL <= 4
+# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 3
+# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 2
+# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+#if MINIMUM_X86_ISA_LEVEL <= 1
+# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
+# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
+# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
+#endif
+
+#ifndef return_X86_OPTIMIZE_V4
+# define X86_IFUNC_IMPL_ADD_V4(...)
+# define return_X86_OPTIMIZE_V4(...) (void) (0)
+# define return_X86_OPTIMIZE1_V4(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V3
+# define X86_IFUNC_IMPL_ADD_V3(...)
+# define return_X86_OPTIMIZE_V3(...) (void) (0)
+# define return_X86_OPTIMIZE1_V3(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V2
+# define X86_IFUNC_IMPL_ADD_V2(...)
+# define return_X86_OPTIMIZE_V2(...) (void) (0)
+# define return_X86_OPTIMIZE1_V2(...) (void) (0)
+#endif
+#ifndef return_X86_OPTIMIZE_V1
+# define X86_IFUNC_IMPL_ADD_V1(...)
+# define return_X86_OPTIMIZE_V1(...) (void) (0)
+# define return_X86_OPTIMIZE1_V1(...) (void) (0)
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 4
+__errordecl (
+ __unreachable_isa_above_4,
+ "This code should be unreachable if ISA level >= 4 build ");
+# define X86_ERROR_IF_REACHABLE_V4() __unreachable_isa_above_4 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V4()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 3
+__errordecl (__unreachable_isa_above_3,
+ "This code should be unreachable if ISA level >= 3 build");
+# define X86_ERROR_IF_REACHABLE_V3() __unreachable_isa_above_3 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V3()
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL >= 2
+__errordecl (__unreachable_isa_above_2,
+ "This code should be unreachable if ISA level >= 2 build");
+# define X86_ERROR_IF_REACHABLE_V2() __unreachable_isa_above_2 ();
+#else
+# define X86_ERROR_IF_REACHABLE_V2()
+#endif
+
+#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
+ ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
+
+#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURE_USABLE_P (ptr, name))
+
+#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
+ (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
+ || CPU_FEATURES_ARCH_P (ptr, name))
+
+#endif
diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
index 09cd72ab20..5b7a2da870 100644
--- a/sysdeps/x86/isa-level.c
+++ b/sysdeps/x86/isa-level.c
@@ -26,38 +26,31 @@
<https://www.gnu.org/licenses/>. */
#include <elf.h>
-
+#include <sysdeps/x86/isa-level.h>
/* ELF program property for x86 ISA level. */
#ifdef INCLUDE_X86_ISA_LEVEL
-# if defined __SSE__ && defined __SSE2__
+# if MINIMUM_X86_ISA_LEVEL >= 1
/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
# define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
# else
# define ISA_BASELINE 0
# endif
-# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
- && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
- && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
- && defined __SSE4_2__
+# if MINIMUM_X86_ISA_LEVEL >= 2
/* NB: ISAs in x86-64 ISA level v2 are used. */
# define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
# else
# define ISA_V2 0
# endif
-# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
- && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
- && defined __BMI__ && defined __BMI2__
+# if MINIMUM_X86_ISA_LEVEL >= 3
/* NB: ISAs in x86-64 ISA level v3 are used. */
# define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
# else
# define ISA_V3 0
# endif
-# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
- && defined __AVX512CD__ && defined __AVX512DQ__ \
- && defined __AVX512VL__
+# if MINIMUM_X86_ISA_LEVEL >= 4
/* NB: ISAs in x86-64 ISA level v4 are used. */
# define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
# else
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
new file mode 100644
index 0000000000..21366b3132
--- /dev/null
+++ b/sysdeps/x86/isa-level.h
@@ -0,0 +1,99 @@
+/* Header defining the minimum x86 ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ In addition to the permissions in the GNU Lesser General Public
+ License, the Free Software Foundation gives you unlimited
+ permission to link the compiled version of this file with other
+ programs, and to distribute those programs without any restriction
+ coming from the use of this file. (The Lesser General Public
+ License restrictions do apply in other respects; for example, they
+ cover modification of the file, and distribution when not linked
+ into another program.)
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _ISA_LEVEL_H
+#define _ISA_LEVEL_H
+
+#if defined __SSE__ && defined __SSE2__
+/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
+# define __X86_ISA_V1 1
+#else
+# define __X86_ISA_V1 0
+#endif
+
+#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
+ && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
+ && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
+/* NB: ISAs in x86-64 ISA level v2 are used. */
+# define __X86_ISA_V2 1
+#else
+# define __X86_ISA_V2 0
+#endif
+
+#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
+ && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
+ && defined __BMI__ && defined __BMI2__
+/* NB: ISAs in x86-64 ISA level v3 are used. */
+# define __X86_ISA_V3 1
+#else
+# define __X86_ISA_V3 0
+#endif
+
+#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
+ && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
+/* NB: ISAs in x86-64 ISA level v4 are used. */
+# define __X86_ISA_V4 1
+#else
+# define __X86_ISA_V4 0
+#endif
+
+#define MINIMUM_X86_ISA_LEVEL \
+ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
+
+
+/*
+ * CPU Features that are hard coded as enabled depending on ISA build
+ * level.
+ * - Values > 0 features are always ENABLED if:
+ * Value >= MINIMUM_X86_ISA_LEVEL
+ */
+
+
+/* ISA level >= 4 guaranteed includes. */
+#define AVX512VL_X86_ISA_LEVEL 4
+#define AVX512BW_X86_ISA_LEVEL 4
+
+/* ISA level >= 3 guaranteed includes. */
+#define AVX2_X86_ISA_LEVEL 3
+#define BMI2_X86_ISA_LEVEL 3
+
+/*
+ * NB: This may not be fully assumable for ISA level >= 3. From
+ * looking over the architectures supported in cpu-features.h the
+ * following CPUs may have an issue with this being default set:
+ * - AMD Excavator
+ */
+#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
+
+/*
+ * KNL (the only cpu that sets this supported in cpu-features.h)
+ * builds with ISA V1 so this shouldn't harm any architectures.
+ */
+#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+
+
+#endif
diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
new file mode 100644
index 0000000000..34634668e5
--- /dev/null
+++ b/sysdeps/x86_64/isa-default-impl.h
@@ -0,0 +1,49 @@
+/* Utility for including proper default function based on ISA level
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include <isa-level.h>
+
+#ifndef DEFAULT_IMPL_V1
+# error "Must have at least ISA V1 Version"
+#endif
+
+#ifndef DEFAULT_IMPL_V2
+# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
+#endif
+
+#ifndef DEFAULT_IMPL_V3
+# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
+#endif
+
+#ifndef DEFAULT_IMPL_V4
+# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
+#endif
+
+#if MINIMUM_X86_ISA_LEVEL == 1
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
+#elif MINIMUM_X86_ISA_LEVEL == 2
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
+#elif MINIMUM_X86_ISA_LEVEL == 3
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
+#elif MINIMUM_X86_ISA_LEVEL == 4
+# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
+#else
+# error "Unsupported ISA Level!"
+#endif
+
+#include ISA_DEFAULT_IMPL
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 2:49 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
@ 2022-06-22 4:47 ` Noah Goldstein
0 siblings, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 4:47 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Tue, Jun 21, 2022 at 7:49 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Tue, Jun 21, 2022 at 7:08 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Factor out some of the ISA level defines in isa-level.c to
> > standalone header isa-level.h
> >
> > 2. Add new headers with ISA level dependent macros for handling
> > ifuncs.
> >
> > Note, this file does not change any code.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > ---
> > sysdeps/x86/init-arch.h | 5 +-
> > sysdeps/x86/isa-cpu-feature-checks.h | 60 ++++++++++++++
> > sysdeps/x86/isa-ifunc-macros.h | 113 +++++++++++++++++++++++++++
> > sysdeps/x86/isa-level.c | 17 ++--
> > sysdeps/x86/isa-level.h | 67 ++++++++++++++++
> > sysdeps/x86_64/isa-default-impl.h | 49 ++++++++++++
> > 6 files changed, 298 insertions(+), 13 deletions(-)
> > create mode 100644 sysdeps/x86/isa-cpu-feature-checks.h
> > create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> > create mode 100644 sysdeps/x86/isa-level.h
> > create mode 100644 sysdeps/x86_64/isa-default-impl.h
> >
> > diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> > index 277c15f116..a9fb4a1975 100644
> > --- a/sysdeps/x86/init-arch.h
> > +++ b/sysdeps/x86/init-arch.h
> > @@ -19,7 +19,10 @@
> > #include <ifunc-init.h>
> > #include <isa.h>
> >
> > -#ifndef __x86_64__
> > +#ifdef __x86_64__
> > +# include <isa-ifunc-macros.h>
> > +# include <isa-cpu-feature-checks.h>
> > +#else
> > /* Due to the reordering and the other nifty extensions in i686, it is
> > not really good to use heavily i586 optimized code on an i686. It's
> > better to use i486 code if it isn't an i586. */
> > diff --git a/sysdeps/x86/isa-cpu-feature-checks.h b/sysdeps/x86/isa-cpu-feature-checks.h
> > new file mode 100644
> > index 0000000000..1bc02ab5b5
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-cpu-feature-checks.h
> > @@ -0,0 +1,60 @@
> > +/* Common ifunc selection utils
> > + All versions must be listed in ifunc-impl-list.c.
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_CPU_FEATURE_CHECKS_H
> > +#define _ISA_CPU_FEATURE_CHECKS_H 1
> > +
> > +/*
> > + * CPU Features that are hard coded as enabled depending on ISA build
> > + * level.
> > + * - Values > 0 features are always ENABLED if:
> > + * Value >= MINIMUM_X86_ISA_LEVEL
> > + */
> > +
> > +#include <isa-level.h>
> > +
> > +/* ISA level >= 4 guaranteed includes. */
> > +#define AVX512VL_X86_ISA_LEVEL 4
> > +#define AVX512BW_X86_ISA_LEVEL 4
> > +
> > +/* ISA level >= 3 guaranteed includes. */
> > +#define AVX2_X86_ISA_LEVEL 3
> > +#define BMI2_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * NB: This may not be fully assumable for ISA level >= 3. From
> > + * looking over the architectures supported in cpu-features.h the
> > + * following CPUs may have an issue with this being default set:
> > + * - AMD Excavator
> > + */
> > +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * KNL (the only cpu that sets this supported in cpu-features.h)
> > + * builds with ISA V1 so this shouldn't harm any architectures.
> > + */
> > +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * ISA independent non-guaranteed includes. Set value at 255 which is
> > + * greater than any foreseeable ISA level.
> > + */
> > +#define RTM_X86_ISA_LEVEL 255
>
> No need for this. We shouldn't blindly change CPU_FEATURE_USABLE_P.
>
> These macros belong to isa-level.h.
Okay. Done in V7.
>
> > +#endif
> > diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> > new file mode 100644
> > index 0000000000..1d1cd99e74
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-ifunc-macros.h
> > @@ -0,0 +1,113 @@
> > +/* Common ifunc selection utils
> > + All versions must be listed in ifunc-impl-list.c.
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_IFUNC_MACROS_H
> > +#define _ISA_IFUNC_MACROS_H 1
> > +
> > +#include <isa-level.h>
> > +#include <sys/cdefs.h>
> > +#include <stdlib.h>
> > +
> > +/* Only include at the level of the minimum build ISA or higher. I.e
> > + if built with ISA=V1, then include all implementations. On the
> > + other hand if built with ISA=V3 only include V3/V4
> > + implementations. If there is no implementation at or above the
> > + minimum build ISA level, then include the highest ISA level
> > + implementation. */
> > +#if MINIMUM_X86_ISA_LEVEL <= 4
> > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 3
> > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 2
> > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 1
> > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +
> > +#ifndef return_X86_OPTIMIZE_V4
> > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V3
> > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V2
> > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V1
> > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 4
> > +__errordecl (
> > + __unreachable_isa_above_4,
> > + "This code should be unreachable if ISA level >= 4 build ");
> > +# define X86_ERROR_IF_REACHABLE_V4() \
> > + __unreachable_isa_above_4 ();
> > +#else
> > +# define X86_ERROR_IF_REACHABLE_V4()
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 3
> > +__errordecl (__unreachable_isa_above_3,
> > + "This code should be unreachable if ISA level >= 3 build");
> > +# define X86_ERROR_IF_REACHABLE_V3() \
> > + __unreachable_isa_above_3 ();
> > +#else
> > +# define X86_ERROR_IF_REACHABLE_V3()
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 2
> > +__errordecl (__unreachable_isa_above_2,
> > + "This code should be unreachable if ISA level >= 2 build");
> > +# define X86_ERROR_IF_REACHABLE_V2() \
> > + __unreachable_isa_above_2 ();#else
> ^^^ Wrong place
Fixed in V7 (that macro is unused right now).
> > +# define X86_ERROR_IF_REACHABLE_V2()
> > +#endif
> > +
> > +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> > + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> > +
> > +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > + || CPU_FEATURE_USABLE_P (ptr, name))
> > +
> > +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > + || CPU_FEATURES_ARCH_P (ptr, name))
> > +
> > +#endif
> > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > index 09cd72ab20..5b7a2da870 100644
> > --- a/sysdeps/x86/isa-level.c
> > +++ b/sysdeps/x86/isa-level.c
> > @@ -26,38 +26,31 @@
> > <https://www.gnu.org/licenses/>. */
> >
> > #include <elf.h>
> > -
> > +#include <sysdeps/x86/isa-level.h>
> > /* ELF program property for x86 ISA level. */
> > #ifdef INCLUDE_X86_ISA_LEVEL
> > -# if defined __SSE__ && defined __SSE2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 1
> > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > # else
> > # define ISA_BASELINE 0
> > # endif
> >
> > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > - && defined __SSE4_2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 2
> > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > # else
> > # define ISA_V2 0
> > # endif
> >
> > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > - && defined __BMI__ && defined __BMI2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 3
> > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > # else
> > # define ISA_V3 0
> > # endif
> >
> > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > - && defined __AVX512VL__
> > +# if MINIMUM_X86_ISA_LEVEL >= 4
> > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > # else
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > new file mode 100644
> > index 0000000000..33dec72bde
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -0,0 +1,67 @@
> > +/* Header defining the minimum x86 ISA level
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + In addition to the permissions in the GNU Lesser General Public
> > + License, the Free Software Foundation gives you unlimited
> > + permission to link the compiled version of this file with other
> > + programs, and to distribute those programs without any restriction
> > + coming from the use of this file. (The Lesser General Public
> > + License restrictions do apply in other respects; for example, they
> > + cover modification of the file, and distribution when not linked
> > + into another program.)
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_LEVEL_H
> > +#define _ISA_LEVEL_H
> > +
> > +#if defined __SSE__ && defined __SSE2__
> > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > +# define __X86_ISA_V1 1
> > +#else
> > +# define __X86_ISA_V1 0
> > +#endif
> > +
> > +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> > + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > +# define __X86_ISA_V2 1
> > +#else
> > +# define __X86_ISA_V2 0
> > +#endif
> > +
> > +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > + && defined __BMI__ && defined __BMI2__
> > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > +# define __X86_ISA_V3 1
> > +#else
> > +# define __X86_ISA_V3 0
> > +#endif
> > +
> > +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > +# define __X86_ISA_V4 1
> > +#else
> > +# define __X86_ISA_V4 0
> > +#endif
> > +
> > +#define MINIMUM_X86_ISA_LEVEL \
> > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > +
> > +#endif
> > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > new file mode 100644
> > index 0000000000..db0635c8e7
> > --- /dev/null
> > +++ b/sysdeps/x86_64/isa-default-impl.h
> > @@ -0,0 +1,49 @@
> > +/* Utility for including proper default function based on ISA level
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include <isa-level.h>
> > +
> > +#ifndef DEFAULT_IMPL_V1
> > +# error "Must have at least ISA V1 Version"
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V2
> > +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V3
> > +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V4
> > +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL == 1
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> > +#elif MINIMUM_X86_ISA_LEVEL == 2
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> > +#elif MINIMUM_X86_ISA_LEVEL == 3
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> > +#elif MINIMUM_X86_ISA_LEVEL == 4
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> > +#else
> > +# error "Unsupport ISA Level!"
> > +#endif
> > +
> > +#include ISA_DEFAULT_IMPL
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v7 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level
2022-06-22 4:47 ` [PATCH v7 " Noah Goldstein
@ 2022-06-22 4:47 ` Noah Goldstein
2022-06-22 14:19 ` [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
1 sibling, 0 replies; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 4:47 UTC (permalink / raw)
To: libc-alpha
1. Refactor files so that all implementations for in the multiarch
directory.
- Essentially moved sse2 {raw|w}memchr.S implementation to
multiarch/{raw|w}memchr-sse2.S
- The non-multiarch {raw|w}memchr.S file now only includes one of
the implementations in the multiarch directory based on the
compiled ISA level (only used for non-multiarch builds.
Otherwise we go through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memchr-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memchr-evex{-rtm}.S).
3. Add new multiarch/rtld-{raw}memchr.S that just include the
non-multiarch {raw}memchr.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
- Guranteed replacement essentially means that for any ISA level
build there must be a function that the baseline of the ISA
supports. So for {raw|w}memchr.S since there is not ISA level 2
function, the ISA level 2 build still includes the ISA level
1 (sse2) function. Once we reach the ISA level 3 build, however,
{raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA
level 1 implementation ({raw|w}memchr-sse2.S) will not be built.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
---
sysdeps/x86_64/memchr.S | 355 +----------------
sysdeps/x86_64/multiarch/ifunc-evex.h | 41 +-
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++--
sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +-
sysdeps/x86_64/multiarch/memchr-evex.S | 10 +-
sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++-
sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++-
sysdeps/x86_64/multiarch/rtld-memchr.S | 18 +
sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 +
sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +-
sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +-
sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +-
sysdeps/x86_64/rawmemchr.S | 186 +--------
sysdeps/x86_64/wmemchr.S | 24 ++
20 files changed, 778 insertions(+), 612 deletions(-)
create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S
create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S
create mode 100644 sysdeps/x86_64/wmemchr.S
diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S
index a160fd9b00..018bb06f04 100644
--- a/sysdeps/x86_64/memchr.S
+++ b/sysdeps/x86_64/memchr.S
@@ -15,358 +15,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define MEMCHR memchr
-#ifdef USE_AS_WMEMCHR
-# define MEMCHR wmemchr
-# define PCMPEQ pcmpeqd
-# define CHAR_PER_VEC 4
-#else
-# define MEMCHR memchr
-# define PCMPEQ pcmpeqb
-# define CHAR_PER_VEC 16
-#endif
+#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S"
-/* fast SSE2 version with using pmaxub and 64 byte loop */
+#include "isa-default-impl.h"
- .text
-ENTRY(MEMCHR)
- movd %esi, %xmm1
- mov %edi, %ecx
-
-#ifdef __ILP32__
- /* Clear the upper 32 bits. */
- movl %edx, %edx
-#endif
-#ifdef USE_AS_WMEMCHR
- test %RDX_LP, %RDX_LP
- jz L(return_null)
-#else
- punpcklbw %xmm1, %xmm1
- test %RDX_LP, %RDX_LP
- jz L(return_null)
- punpcklbw %xmm1, %xmm1
-#endif
-
- and $63, %ecx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %ecx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %rdx
- jbe L(return_null)
- add $16, %rdi
- and $15, %ecx
- and $-16, %rdi
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %ecx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- PCMPEQ %xmm1, %xmm0
- /* Check if there is a match. */
- pmovmskb %xmm0, %eax
- /* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
- /* Check which byte is a match. */
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
- "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
- possible addition overflow. */
- neg %rcx
- add $16, %rcx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- sub %rcx, %rdx
- jbe L(return_null)
- add $16, %rdi
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- PCMPEQ %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- mov %rdi, %rcx
- and $-64, %rdi
- and $63, %ecx
-#ifdef USE_AS_WMEMCHR
- shr $2, %ecx
-#endif
- add %rcx, %rdx
-
- .p2align 4
-L(align64_loop):
- sub $(CHAR_PER_VEC * 4), %rdx
- jbe L(exit_loop)
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- PCMPEQ %xmm1, %xmm0
- PCMPEQ %xmm1, %xmm2
- PCMPEQ %xmm1, %xmm3
- PCMPEQ %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(exit_loop):
- add $(CHAR_PER_VEC * 2), %edx
- jle L(exit_loop_32)
-
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- PCMPEQ %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- PCMPEQ %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32_1)
- sub $CHAR_PER_VEC, %edx
- jle L(return_null)
-
- PCMPEQ 48(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches48_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(exit_loop_32):
- add $(CHAR_PER_VEC * 2), %edx
- movdqa (%rdi), %xmm0
- PCMPEQ %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches_1)
- sub $CHAR_PER_VEC, %edx
- jbe L(return_null)
-
- PCMPEQ 16(%rdi), %xmm1
- pmovmskb %xmm1, %eax
- test %eax, %eax
- jnz L(matches16_1)
- xor %eax, %eax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 16(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches32_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 32(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches48_1):
- bsf %eax, %eax
-#ifdef USE_AS_WMEMCHR
- mov %eax, %esi
- shr $2, %esi
- sub %rsi, %rdx
-#else
- sub %rax, %rdx
-#endif
- jbe L(return_null)
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(return_null):
- xor %eax, %eax
- ret
-END(MEMCHR)
-
-#ifndef USE_AS_WMEMCHR
strong_alias (memchr, __memchr)
libc_hidden_builtin_def(memchr)
-#endif
diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h
index b8f7a12ea2..24d24b4df1 100644
--- a/sysdeps/x86_64/multiarch/ifunc-evex.h
+++ b/sysdeps/x86_64/multiarch/ifunc-evex.h
@@ -19,37 +19,48 @@
#include <init-arch.h>
-extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
-extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden;
extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden;
+extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden;
+
+/* TODO: Look into using the ISA build level to remove some/all of the
+ feature checks. */
static inline void *
IFUNC_SELECTOR (void)
{
- const struct cpu_features* cpu_features = __get_cpu_features ();
+ const struct cpu_features *cpu_features = __get_cpu_features ();
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
- && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
- && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
+ && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ AVX_Fast_Unaligned_Load))
{
- if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
- && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
+ if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
+ && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
{
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (evex_rtm);
+ return_X86_OPTIMIZE_V4 (evex_rtm);
- return OPTIMIZE (evex);
+ return_X86_OPTIMIZE_V4 (evex);
}
+ X86_ERROR_IF_REACHABLE_V4 ();
+
if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
- return OPTIMIZE (avx2_rtm);
+ return_X86_OPTIMIZE_V3 (avx2_rtm);
- if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
- return OPTIMIZE (avx2);
+ if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
+ Prefer_No_VZEROUPPER))
+ return_X86_OPTIMIZE_V3 (avx2);
}
- return OPTIMIZE (sse2);
+ X86_ERROR_IF_REACHABLE_V3 ();
+
+ /* This is unreachable (compile time checked) if ISA level >= 3
+ so no need for a robust fallback here. */
+ return_X86_OPTIMIZE_V2 (sse2);
}
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 883362f63d..bf52cf96d0 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -25,7 +25,8 @@
/* Fill ARRAY of MAX elements with IFUNC implementations for function
NAME supported on target machine and return the number of valid
- entries. */
+ entries. Each set of implementations for a given function is sorted in
+ descending order by ISA level. */
size_t
__libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
@@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
- IFUNC_IMPL_ADD (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
- IFUNC_IMPL_ADD (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex)
- IFUNC_IMPL_ADD (array, i, memchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__memchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex)
- IFUNC_IMPL_ADD (array, i, rawmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__rawmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
- IFUNC_IMPL_ADD (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
- IFUNC_IMPL_ADD (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex)
- IFUNC_IMPL_ADD (array, i, wmemchr,
+ X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
(CPU_FEATURE_USABLE (AVX512VL)
&& CPU_FEATURE_USABLE (AVX512BW)
&& CPU_FEATURE_USABLE (BMI2)),
__wmemchr_evex_rtm)
- IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2))
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
+ X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* Can be lowered to V1 if a V2 implementation is added. */
+ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S
index c5a256eb37..691662f0fb 100644
--- a/sysdeps/x86_64/multiarch/memchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memchr-avx2.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 0fd11b7632..10ed0434ae 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -16,7 +16,15 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
+#endif
+
+#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
# include <sysdep.h>
diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S
index 2c6fdd41d6..acd5c15e22 100644
--- a/sysdeps/x86_64/multiarch/memchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memchr-sse2.S
@@ -16,13 +16,367 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#if IS_IN (libc)
-# define memchr __memchr_sse2
+#include <isa-level.h>
-# undef strong_alias
-# define strong_alias(memchr, __memchr)
-# undef libc_hidden_builtin_def
-# define libc_hidden_builtin_def(memchr)
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../memchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef MEMCHR
+# define MEMCHR __memchr_sse2
+# endif
+# ifdef USE_AS_WMEMCHR
+# define PCMPEQ pcmpeqd
+# define CHAR_PER_VEC 4
+# else
+# define PCMPEQ pcmpeqb
+# define CHAR_PER_VEC 16
+# endif
+
+/* fast SSE2 version with using pmaxub and 64 byte loop */
+
+ .text
+ENTRY(MEMCHR)
+ movd %esi, %xmm1
+ mov %edi, %ecx
+
+# ifdef __ILP32__
+ /* Clear the upper 32 bits. */
+ movl %edx, %edx
+# endif
+# ifdef USE_AS_WMEMCHR
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+# else
+ punpcklbw %xmm1, %xmm1
+ test %RDX_LP, %RDX_LP
+ jz L(return_null)
+ punpcklbw %xmm1, %xmm1
+# endif
+
+ and $63, %ecx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %ecx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ and $15, %ecx
+ and $-16, %rdi
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %ecx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ PCMPEQ %xmm1, %xmm0
+ /* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ /* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+ /* Check which byte is a match. */
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using
+ "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void
+ possible addition overflow. */
+ neg %rcx
+ add $16, %rcx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ sub %rcx, %rdx
+ jbe L(return_null)
+ add $16, %rdi
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ PCMPEQ %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ mov %rdi, %rcx
+ and $-64, %rdi
+ and $63, %ecx
+# ifdef USE_AS_WMEMCHR
+ shr $2, %ecx
+# endif
+ add %rcx, %rdx
+
+ .p2align 4
+L(align64_loop):
+ sub $(CHAR_PER_VEC * 4), %rdx
+ jbe L(exit_loop)
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ PCMPEQ %xmm1, %xmm0
+ PCMPEQ %xmm1, %xmm2
+ PCMPEQ %xmm1, %xmm3
+ PCMPEQ %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(exit_loop):
+ add $(CHAR_PER_VEC * 2), %edx
+ jle L(exit_loop_32)
+
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ PCMPEQ %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ PCMPEQ %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32_1)
+ sub $CHAR_PER_VEC, %edx
+ jle L(return_null)
+
+ PCMPEQ 48(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches48_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(exit_loop_32):
+ add $(CHAR_PER_VEC * 2), %edx
+ movdqa (%rdi), %xmm0
+ PCMPEQ %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches_1)
+ sub $CHAR_PER_VEC, %edx
+ jbe L(return_null)
+
+ PCMPEQ 16(%rdi), %xmm1
+ pmovmskb %xmm1, %eax
+ test %eax, %eax
+ jnz L(matches16_1)
+ xor %eax, %eax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 16(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches32_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 32(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches48_1):
+ bsf %eax, %eax
+# ifdef USE_AS_WMEMCHR
+ mov %eax, %esi
+ shr $2, %esi
+ sub %rsi, %rdx
+# else
+ sub %rax, %rdx
+# endif
+ jbe L(return_null)
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(return_null):
+ xor %eax, %eax
+ ret
+END(MEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
index acc5f6e2fb..5c1dcd3ca7 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
index 128f9ea637..d6bff28757 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_avx2
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_avx2
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
index deda1ca395..8ff7f27c9c 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __rawmemchr_evex_rtm
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex_rtm
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index ec942b77ba..dc1c450699 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __rawmemchr_evex
-#define USE_AS_RAWMEMCHR 1
+#ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_evex
+#endif
+#define USE_AS_RAWMEMCHR 1
+#define MEMCHR RAWMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
index 3841c14c34..73f4fa9589 100644
--- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S
@@ -16,14 +16,199 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-/* Define multiple versions only for the definition in libc. */
-#if IS_IN (libc)
-# define __rawmemchr __rawmemchr_sse2
-
-# undef weak_alias
-# define weak_alias(__rawmemchr, rawmemchr)
-# undef libc_hidden_def
-# define libc_hidden_def(__rawmemchr)
+#include <isa-level.h>
+
+#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL
+# error "Multiarch build should never default include!"
#endif
-#include "../rawmemchr.S"
+/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we
+ need this to build for ISA V2 builds. */
+#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \
+ || defined ISA_DEFAULT_IMPL
+
+
+# include <sysdep.h>
+
+# ifndef RAWMEMCHR
+# define RAWMEMCHR __rawmemchr_sse2
+# endif
+
+ .text
+ENTRY (RAWMEMCHR)
+ movd %rsi, %xmm1
+ mov %rdi, %rcx
+
+ punpcklbw %xmm1, %xmm1
+ punpcklbw %xmm1, %xmm1
+
+ and $63, %rcx
+ pshufd $0, %xmm1, %xmm1
+
+ cmp $48, %rcx
+ ja L(crosscache)
+
+ movdqu (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+
+ jnz L(matches)
+ add $16, %rdi
+ and $-16, %rdi
+ jmp L(loop_prolog)
+
+ .p2align 4
+L(crosscache):
+ and $15, %rcx
+ and $-16, %rdi
+ movdqa (%rdi), %xmm0
+
+ pcmpeqb %xmm1, %xmm0
+/* Check if there is a match. */
+ pmovmskb %xmm0, %eax
+/* Remove the leading bytes. */
+ sar %cl, %eax
+ test %eax, %eax
+ je L(unaligned_no_match)
+/* Check which byte is a match. */
+ bsf %eax, %eax
+
+ add %rdi, %rax
+ add %rcx, %rax
+ ret
+
+ .p2align 4
+L(unaligned_no_match):
+ add $16, %rdi
+
+ .p2align 4
+L(loop_prolog):
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm4
+ pcmpeqb %xmm1, %xmm4
+ add $64, %rdi
+ pmovmskb %xmm4, %eax
+ test %eax, %eax
+ jnz L(matches0)
+
+ test $0x3f, %rdi
+ jz L(align64_loop)
+
+ movdqa (%rdi), %xmm0
+ pcmpeqb %xmm1, %xmm0
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ movdqa 16(%rdi), %xmm2
+ pcmpeqb %xmm1, %xmm2
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ movdqa 48(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+ pmovmskb %xmm3, %eax
+
+ add $64, %rdi
+ test %eax, %eax
+ jnz L(matches0)
+
+ and $-64, %rdi
+
+ .p2align 4
+L(align64_loop):
+ movdqa (%rdi), %xmm0
+ movdqa 16(%rdi), %xmm2
+ movdqa 32(%rdi), %xmm3
+ movdqa 48(%rdi), %xmm4
+
+ pcmpeqb %xmm1, %xmm0
+ pcmpeqb %xmm1, %xmm2
+ pcmpeqb %xmm1, %xmm3
+ pcmpeqb %xmm1, %xmm4
+
+ pmaxub %xmm0, %xmm3
+ pmaxub %xmm2, %xmm4
+ pmaxub %xmm3, %xmm4
+ pmovmskb %xmm4, %eax
+
+ add $64, %rdi
+
+ test %eax, %eax
+ jz L(align64_loop)
+
+ sub $64, %rdi
+
+ pmovmskb %xmm0, %eax
+ test %eax, %eax
+ jnz L(matches)
+
+ pmovmskb %xmm2, %eax
+ test %eax, %eax
+ jnz L(matches16)
+
+ movdqa 32(%rdi), %xmm3
+ pcmpeqb %xmm1, %xmm3
+
+ pcmpeqb 48(%rdi), %xmm1
+ pmovmskb %xmm3, %eax
+ test %eax, %eax
+ jnz L(matches32)
+
+ pmovmskb %xmm1, %eax
+ bsf %eax, %eax
+ lea 48(%rdi, %rax), %rax
+ ret
+
+ .p2align 4
+L(matches0):
+ bsf %eax, %eax
+ lea -16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches):
+ bsf %eax, %eax
+ add %rdi, %rax
+ ret
+
+ .p2align 4
+L(matches16):
+ bsf %eax, %eax
+ lea 16(%rax, %rdi), %rax
+ ret
+
+ .p2align 4
+L(matches32):
+ bsf %eax, %eax
+ lea 32(%rax, %rdi), %rax
+ ret
+
+END (RAWMEMCHR)
+#endif
diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S
new file mode 100644
index 0000000000..a14b192bed
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-memchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../memchr.S"
diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
new file mode 100644
index 0000000000..5d4110a052
--- /dev/null
+++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S
@@ -0,0 +1,18 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "../rawmemchr.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
index 58ed21db01..2a1cff5b05 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
index 282854f1a1..2bf93fd84b 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_avx2
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_avx2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-avx2.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
index a346cd35a1..c67309e8a1 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S
@@ -1,3 +1,7 @@
-#define MEMCHR __wmemchr_evex_rtm
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex_rtm
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
#include "memchr-evex-rtm.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S
index 06cd0f9f5a..5512d5cdc3 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-evex.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S
@@ -1,4 +1,7 @@
-#define MEMCHR __wmemchr_evex
-#define USE_AS_WMEMCHR 1
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_evex
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
#include "memchr-evex.S"
diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
index 70a965d552..3081fb6821 100644
--- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S
@@ -1,4 +1,25 @@
-#define USE_AS_WMEMCHR 1
-#define wmemchr __wmemchr_sse2
+/* wmemchr optimized with SSE2
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
-#include "../memchr.S"
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef WMEMCHR
+# define WMEMCHR __wmemchr_sse2
+#endif
+#define USE_AS_WMEMCHR 1
+#define MEMCHR WMEMCHR
+
+#include "memchr-sse2.S"
diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S
index 4c1a3383b9..e401a2ac53 100644
--- a/sysdeps/x86_64/rawmemchr.S
+++ b/sysdeps/x86_64/rawmemchr.S
@@ -17,185 +17,13 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#include <sysdep.h>
+#define RAWMEMCHR rawmemchr
- .text
-ENTRY (__rawmemchr)
- movd %rsi, %xmm1
- mov %rdi, %rcx
+#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S"
- punpcklbw %xmm1, %xmm1
- punpcklbw %xmm1, %xmm1
+#include "isa-default-impl.h"
- and $63, %rcx
- pshufd $0, %xmm1, %xmm1
-
- cmp $48, %rcx
- ja L(crosscache)
-
- movdqu (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
- test %eax, %eax
-
- jnz L(matches)
- add $16, %rdi
- and $-16, %rdi
- jmp L(loop_prolog)
-
- .p2align 4
-L(crosscache):
- and $15, %rcx
- and $-16, %rdi
- movdqa (%rdi), %xmm0
-
- pcmpeqb %xmm1, %xmm0
-/* Check if there is a match. */
- pmovmskb %xmm0, %eax
-/* Remove the leading bytes. */
- sar %cl, %eax
- test %eax, %eax
- je L(unaligned_no_match)
-/* Check which byte is a match. */
- bsf %eax, %eax
-
- add %rdi, %rax
- add %rcx, %rax
- ret
-
- .p2align 4
-L(unaligned_no_match):
- add $16, %rdi
-
- .p2align 4
-L(loop_prolog):
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm4
- pcmpeqb %xmm1, %xmm4
- add $64, %rdi
- pmovmskb %xmm4, %eax
- test %eax, %eax
- jnz L(matches0)
-
- test $0x3f, %rdi
- jz L(align64_loop)
-
- movdqa (%rdi), %xmm0
- pcmpeqb %xmm1, %xmm0
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- movdqa 16(%rdi), %xmm2
- pcmpeqb %xmm1, %xmm2
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- movdqa 48(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
- pmovmskb %xmm3, %eax
-
- add $64, %rdi
- test %eax, %eax
- jnz L(matches0)
-
- and $-64, %rdi
-
- .p2align 4
-L(align64_loop):
- movdqa (%rdi), %xmm0
- movdqa 16(%rdi), %xmm2
- movdqa 32(%rdi), %xmm3
- movdqa 48(%rdi), %xmm4
-
- pcmpeqb %xmm1, %xmm0
- pcmpeqb %xmm1, %xmm2
- pcmpeqb %xmm1, %xmm3
- pcmpeqb %xmm1, %xmm4
-
- pmaxub %xmm0, %xmm3
- pmaxub %xmm2, %xmm4
- pmaxub %xmm3, %xmm4
- pmovmskb %xmm4, %eax
-
- add $64, %rdi
-
- test %eax, %eax
- jz L(align64_loop)
-
- sub $64, %rdi
-
- pmovmskb %xmm0, %eax
- test %eax, %eax
- jnz L(matches)
-
- pmovmskb %xmm2, %eax
- test %eax, %eax
- jnz L(matches16)
-
- movdqa 32(%rdi), %xmm3
- pcmpeqb %xmm1, %xmm3
-
- pcmpeqb 48(%rdi), %xmm1
- pmovmskb %xmm3, %eax
- test %eax, %eax
- jnz L(matches32)
-
- pmovmskb %xmm1, %eax
- bsf %eax, %eax
- lea 48(%rdi, %rax), %rax
- ret
-
- .p2align 4
-L(matches0):
- bsf %eax, %eax
- lea -16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches):
- bsf %eax, %eax
- add %rdi, %rax
- ret
-
- .p2align 4
-L(matches16):
- bsf %eax, %eax
- lea 16(%rax, %rdi), %rax
- ret
-
- .p2align 4
-L(matches32):
- bsf %eax, %eax
- lea 32(%rax, %rdi), %rax
- ret
-
-END (__rawmemchr)
-
-weak_alias (__rawmemchr, rawmemchr)
-libc_hidden_builtin_def (__rawmemchr)
+strong_alias (rawmemchr, __rawmemchr)
+libc_hidden_builtin_def (rawmemchr)
diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S
new file mode 100644
index 0000000000..dd0490f86b
--- /dev/null
+++ b/sysdeps/x86_64/wmemchr.S
@@ -0,0 +1,24 @@
+/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WMEMCHR wmemchr
+
+#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S"
+#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S"
+#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S"
+
+#include "isa-default-impl.h"
--
2.34.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 4:47 ` [PATCH v7 " Noah Goldstein
2022-06-22 4:47 ` [PATCH v7 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
@ 2022-06-22 14:19 ` H.J. Lu
2022-06-22 15:12 ` Noah Goldstein
1 sibling, 1 reply; 27+ messages in thread
From: H.J. Lu @ 2022-06-22 14:19 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Tue, Jun 21, 2022 at 9:48 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> 1. Factor out some of the ISA level defines in isa-level.c to
> standalone header isa-level.h
>
> 2. Add new headers with ISA level dependent macros for handling
> ifuncs.
>
> Note, this file does not change any code.
>
> Tested with and without multiarch on x86_64 for ISA levels:
> {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> ---
> sysdeps/x86/init-arch.h | 4 +-
> sysdeps/x86/isa-ifunc-macros.h | 111 ++++++++++++++++++++++++++++++
> sysdeps/x86/isa-level.c | 17 ++---
> sysdeps/x86/isa-level.h | 99 ++++++++++++++++++++++++++
> sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++
> 5 files changed, 267 insertions(+), 13 deletions(-)
> create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> create mode 100644 sysdeps/x86/isa-level.h
> create mode 100644 sysdeps/x86_64/isa-default-impl.h
>
> diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> index 277c15f116..a2886a2532 100644
> --- a/sysdeps/x86/init-arch.h
> +++ b/sysdeps/x86/init-arch.h
> @@ -19,7 +19,9 @@
> #include <ifunc-init.h>
> #include <isa.h>
>
> -#ifndef __x86_64__
> +#ifdef __x86_64__
> +# include <isa-ifunc-macros.h>
> +#else
> /* Due to the reordering and the other nifty extensions in i686, it is
> not really good to use heavily i586 optimized code on an i686. It's
> better to use i486 code if it isn't an i586. */
> diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> new file mode 100644
> index 0000000000..2aa8fab000
> --- /dev/null
> +++ b/sysdeps/x86/isa-ifunc-macros.h
> @@ -0,0 +1,111 @@
> +/* Common ifunc selection utils
> + All versions must be listed in ifunc-impl-list.c.
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_IFUNC_MACROS_H
> +#define _ISA_IFUNC_MACROS_H 1
> +
> +#include <isa-level.h>
> +#include <sys/cdefs.h>
> +#include <stdlib.h>
> +
> +/* Only include at the level of the minimum build ISA or higher. I.e
> + if built with ISA=V1, then include all implementations. On the
> + other hand if built with ISA=V3 only include V3/V4
> + implementations. If there is no implementation at or above the
> + minimum build ISA level, then include the highest ISA level
> + implementation. */
> +#if MINIMUM_X86_ISA_LEVEL <= 4
> +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 3
> +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 2
> +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +#if MINIMUM_X86_ISA_LEVEL <= 1
> +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> +#endif
> +
> +#ifndef return_X86_OPTIMIZE_V4
> +# define X86_IFUNC_IMPL_ADD_V4(...)
> +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V3
> +# define X86_IFUNC_IMPL_ADD_V3(...)
> +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V2
> +# define X86_IFUNC_IMPL_ADD_V2(...)
> +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> +#endif
> +#ifndef return_X86_OPTIMIZE_V1
> +# define X86_IFUNC_IMPL_ADD_V1(...)
> +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 4
> +__errordecl (
> + __unreachable_isa_above_4,
> + "This code should be unreachable if ISA level >= 4 build ");
> +# define X86_ERROR_IF_REACHABLE_V4() __unreachable_isa_above_4 ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V4()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 3
> +__errordecl (__unreachable_isa_above_3,
> + "This code should be unreachable if ISA level >= 3 build");
> +# define X86_ERROR_IF_REACHABLE_V3() __unreachable_isa_above_3 ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V3()
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL >= 2
> +__errordecl (__unreachable_isa_above_2,
> + "This code should be unreachable if ISA level >= 2 build");
> +# define X86_ERROR_IF_REACHABLE_V2() __unreachable_isa_above_2 ();
> +#else
> +# define X86_ERROR_IF_REACHABLE_V2()
> +#endif
No need for return_X86_OPTIMIZE nor X86_ERROR_IF_REACHABLE.
When the minimum ISA level is v3, we will get undefined
symbol linker error if compiler doesn't optimize out references
to v1 and v2 symbols.
> +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> +
> +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURE_USABLE_P (ptr, name))
> +
> +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> + || CPU_FEATURES_ARCH_P (ptr, name))
> +
> +#endif
> diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> index 09cd72ab20..5b7a2da870 100644
> --- a/sysdeps/x86/isa-level.c
> +++ b/sysdeps/x86/isa-level.c
> @@ -26,38 +26,31 @@
> <https://www.gnu.org/licenses/>. */
>
> #include <elf.h>
> -
> +#include <sysdeps/x86/isa-level.h>
> /* ELF program property for x86 ISA level. */
> #ifdef INCLUDE_X86_ISA_LEVEL
> -# if defined __SSE__ && defined __SSE2__
> +# if MINIMUM_X86_ISA_LEVEL >= 1
> /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> # else
> # define ISA_BASELINE 0
> # endif
>
> -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> - && defined __SSE4_2__
> +# if MINIMUM_X86_ISA_LEVEL >= 2
> /* NB: ISAs in x86-64 ISA level v2 are used. */
> # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> # else
> # define ISA_V2 0
> # endif
>
> -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> - && defined __BMI__ && defined __BMI2__
> +# if MINIMUM_X86_ISA_LEVEL >= 3
> /* NB: ISAs in x86-64 ISA level v3 are used. */
> # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> # else
> # define ISA_V3 0
> # endif
>
> -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> - && defined __AVX512CD__ && defined __AVX512DQ__ \
> - && defined __AVX512VL__
> +# if MINIMUM_X86_ISA_LEVEL >= 4
> /* NB: ISAs in x86-64 ISA level v4 are used. */
> # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> # else
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> new file mode 100644
> index 0000000000..21366b3132
> --- /dev/null
> +++ b/sysdeps/x86/isa-level.h
> @@ -0,0 +1,99 @@
> +/* Header defining the minimum x86 ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + In addition to the permissions in the GNU Lesser General Public
> + License, the Free Software Foundation gives you unlimited
> + permission to link the compiled version of this file with other
> + programs, and to distribute those programs without any restriction
> + coming from the use of this file. (The Lesser General Public
> + License restrictions do apply in other respects; for example, they
> + cover modification of the file, and distribution when not linked
> + into another program.)
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#ifndef _ISA_LEVEL_H
> +#define _ISA_LEVEL_H
> +
> +#if defined __SSE__ && defined __SSE2__
> +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> +# define __X86_ISA_V1 1
> +#else
> +# define __X86_ISA_V1 0
> +#endif
> +
> +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> +/* NB: ISAs in x86-64 ISA level v2 are used. */
> +# define __X86_ISA_V2 1
> +#else
> +# define __X86_ISA_V2 0
> +#endif
> +
> +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> + && defined __BMI__ && defined __BMI2__
> +/* NB: ISAs in x86-64 ISA level v3 are used. */
> +# define __X86_ISA_V3 1
> +#else
> +# define __X86_ISA_V3 0
> +#endif
> +
> +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> +/* NB: ISAs in x86-64 ISA level v4 are used. */
> +# define __X86_ISA_V4 1
> +#else
> +# define __X86_ISA_V4 0
> +#endif
> +
> +#define MINIMUM_X86_ISA_LEVEL \
> + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> +
> +
> +/*
> + * CPU Features that are hard coded as enabled depending on ISA build
> + * level.
> + * - Values > 0 features are always ENABLED if:
> + * Value >= MINIMUM_X86_ISA_LEVEL
> + */
> +
> +
> +/* ISA level >= 4 guaranteed includes. */
> +#define AVX512VL_X86_ISA_LEVEL 4
> +#define AVX512BW_X86_ISA_LEVEL 4
> +
> +/* ISA level >= 3 guaranteed includes. */
> +#define AVX2_X86_ISA_LEVEL 3
> +#define BMI2_X86_ISA_LEVEL 3
> +
> +/*
> + * NB: This may not be fully assumable for ISA level >= 3. From
> + * looking over the architectures supported in cpu-features.h the
> + * following CPUs may have an issue with this being default set:
> + * - AMD Excavator
> + */
> +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> +
> +/*
> + * KNL (the only cpu that sets this supported in cpu-features.h)
> + * builds with ISA V1 so this shouldn't harm any architectures.
> + */
> +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> +
> +
> +#endif
> diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> new file mode 100644
> index 0000000000..34634668e5
> --- /dev/null
> +++ b/sysdeps/x86_64/isa-default-impl.h
> @@ -0,0 +1,49 @@
> +/* Utility for including proper default function based on ISA level
> + Copyright (C) 2022 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +#include <isa-level.h>
> +
> +#ifndef DEFAULT_IMPL_V1
> +# error "Must have at least ISA V1 Version"
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V2
> +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V3
> +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> +#endif
> +
> +#ifndef DEFAULT_IMPL_V4
> +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> +#endif
> +
> +#if MINIMUM_X86_ISA_LEVEL == 1
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> +#elif MINIMUM_X86_ISA_LEVEL == 2
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> +#elif MINIMUM_X86_ISA_LEVEL == 3
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> +#elif MINIMUM_X86_ISA_LEVEL == 4
> +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> +#else
> +# error "Unsupported ISA Level!"
> +#endif
> +
> +#include ISA_DEFAULT_IMPL
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 14:19 ` [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
@ 2022-06-22 15:12 ` Noah Goldstein
2022-06-22 15:26 ` H.J. Lu
0 siblings, 1 reply; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 15:12 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 7:20 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Tue, Jun 21, 2022 at 9:48 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > 1. Factor out some of the ISA level defines in isa-level.c to
> > standalone header isa-level.h
> >
> > 2. Add new headers with ISA level dependent macros for handling
> > ifuncs.
> >
> > Note, this file does not change any code.
> >
> > Tested with and without multiarch on x86_64 for ISA levels:
> > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > ---
> > sysdeps/x86/init-arch.h | 4 +-
> > sysdeps/x86/isa-ifunc-macros.h | 111 ++++++++++++++++++++++++++++++
> > sysdeps/x86/isa-level.c | 17 ++---
> > sysdeps/x86/isa-level.h | 99 ++++++++++++++++++++++++++
> > sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++
> > 5 files changed, 267 insertions(+), 13 deletions(-)
> > create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> > create mode 100644 sysdeps/x86/isa-level.h
> > create mode 100644 sysdeps/x86_64/isa-default-impl.h
> >
> > diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> > index 277c15f116..a2886a2532 100644
> > --- a/sysdeps/x86/init-arch.h
> > +++ b/sysdeps/x86/init-arch.h
> > @@ -19,7 +19,9 @@
> > #include <ifunc-init.h>
> > #include <isa.h>
> >
> > -#ifndef __x86_64__
> > +#ifdef __x86_64__
> > +# include <isa-ifunc-macros.h>
> > +#else
> > /* Due to the reordering and the other nifty extensions in i686, it is
> > not really good to use heavily i586 optimized code on an i686. It's
> > better to use i486 code if it isn't an i586. */
> > diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> > new file mode 100644
> > index 0000000000..2aa8fab000
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-ifunc-macros.h
> > @@ -0,0 +1,111 @@
> > +/* Common ifunc selection utils
> > + All versions must be listed in ifunc-impl-list.c.
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_IFUNC_MACROS_H
> > +#define _ISA_IFUNC_MACROS_H 1
> > +
> > +#include <isa-level.h>
> > +#include <sys/cdefs.h>
> > +#include <stdlib.h>
> > +
> > +/* Only include at the level of the minimum build ISA or higher. I.e
> > + if built with ISA=V1, then include all implementations. On the
> > + other hand if built with ISA=V3 only include V3/V4
> > + implementations. If there is no implementation at or above the
> > + minimum build ISA level, then include the highest ISA level
> > + implementation. */
> > +#if MINIMUM_X86_ISA_LEVEL <= 4
> > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 3
> > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 2
> > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +#if MINIMUM_X86_ISA_LEVEL <= 1
> > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> > +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> > +#endif
> > +
> > +#ifndef return_X86_OPTIMIZE_V4
> > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V3
> > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V2
> > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> > +#endif
> > +#ifndef return_X86_OPTIMIZE_V1
> > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> > +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 4
> > +__errordecl (
> > + __unreachable_isa_above_4,
> > + "This code should be unreachable if ISA level >= 4 build ");
> > +# define X86_ERROR_IF_REACHABLE_V4() __unreachable_isa_above_4 ();
> > +#else
> > +# define X86_ERROR_IF_REACHABLE_V4()
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 3
> > +__errordecl (__unreachable_isa_above_3,
> > + "This code should be unreachable if ISA level >= 3 build");
> > +# define X86_ERROR_IF_REACHABLE_V3() __unreachable_isa_above_3 ();
> > +#else
> > +# define X86_ERROR_IF_REACHABLE_V3()
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL >= 2
> > +__errordecl (__unreachable_isa_above_2,
> > + "This code should be unreachable if ISA level >= 2 build");
> > +# define X86_ERROR_IF_REACHABLE_V2() __unreachable_isa_above_2 ();
> > +#else
> > +# define X86_ERROR_IF_REACHABLE_V2()
> > +#endif
>
> No need for return_X86_OPTIMIZE nor X86_ERROR_IF_REACHABLE.
> When the minimum ISA level is v3, we will get undefined
> symbol linker error if compiler doesn't optimize out references
> to v1 and v2 symbols.
Prefer to keep both.
Think in this case there is a meaningful clarity argument. If build fails
because undefined reference to sse2 its a less meaningfully error
than if it fails on the exact attr warning.
>
> > +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> > + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> > +
> > +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > + || CPU_FEATURE_USABLE_P (ptr, name))
> > +
> > +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > + || CPU_FEATURES_ARCH_P (ptr, name))
> > +
> > +#endif
> > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > index 09cd72ab20..5b7a2da870 100644
> > --- a/sysdeps/x86/isa-level.c
> > +++ b/sysdeps/x86/isa-level.c
> > @@ -26,38 +26,31 @@
> > <https://www.gnu.org/licenses/>. */
> >
> > #include <elf.h>
> > -
> > +#include <sysdeps/x86/isa-level.h>
> > /* ELF program property for x86 ISA level. */
> > #ifdef INCLUDE_X86_ISA_LEVEL
> > -# if defined __SSE__ && defined __SSE2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 1
> > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > # else
> > # define ISA_BASELINE 0
> > # endif
> >
> > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > - && defined __SSE4_2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 2
> > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > # else
> > # define ISA_V2 0
> > # endif
> >
> > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > - && defined __BMI__ && defined __BMI2__
> > +# if MINIMUM_X86_ISA_LEVEL >= 3
> > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > # else
> > # define ISA_V3 0
> > # endif
> >
> > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > - && defined __AVX512VL__
> > +# if MINIMUM_X86_ISA_LEVEL >= 4
> > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > # else
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > new file mode 100644
> > index 0000000000..21366b3132
> > --- /dev/null
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -0,0 +1,99 @@
> > +/* Header defining the minimum x86 ISA level
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + In addition to the permissions in the GNU Lesser General Public
> > + License, the Free Software Foundation gives you unlimited
> > + permission to link the compiled version of this file with other
> > + programs, and to distribute those programs without any restriction
> > + coming from the use of this file. (The Lesser General Public
> > + License restrictions do apply in other respects; for example, they
> > + cover modification of the file, and distribution when not linked
> > + into another program.)
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#ifndef _ISA_LEVEL_H
> > +#define _ISA_LEVEL_H
> > +
> > +#if defined __SSE__ && defined __SSE2__
> > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > +# define __X86_ISA_V1 1
> > +#else
> > +# define __X86_ISA_V1 0
> > +#endif
> > +
> > +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> > + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > +# define __X86_ISA_V2 1
> > +#else
> > +# define __X86_ISA_V2 0
> > +#endif
> > +
> > +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > + && defined __BMI__ && defined __BMI2__
> > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > +# define __X86_ISA_V3 1
> > +#else
> > +# define __X86_ISA_V3 0
> > +#endif
> > +
> > +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > +# define __X86_ISA_V4 1
> > +#else
> > +# define __X86_ISA_V4 0
> > +#endif
> > +
> > +#define MINIMUM_X86_ISA_LEVEL \
> > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > +
> > +
> > +/*
> > + * CPU Features that are hard coded as enabled depending on ISA build
> > + * level.
> > + * - Values > 0 features are always ENABLED if:
> > + * Value >= MINIMUM_X86_ISA_LEVEL
> > + */
> > +
> > +
> > +/* ISA level >= 4 guaranteed includes. */
> > +#define AVX512VL_X86_ISA_LEVEL 4
> > +#define AVX512BW_X86_ISA_LEVEL 4
> > +
> > +/* ISA level >= 3 guaranteed includes. */
> > +#define AVX2_X86_ISA_LEVEL 3
> > +#define BMI2_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * NB: This may not be fully assumable for ISA level >= 3. From
> > + * looking over the architectures supported in cpu-features.h the
> > + * following CPUs may have an issue with this being default set:
> > + * - AMD Excavator
> > + */
> > +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> > +
> > +/*
> > + * KNL (the only cpu that sets this supported in cpu-features.h)
> > + * builds with ISA V1 so this shouldn't harm any architectures.
> > + */
> > +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > +
> > +
> > +#endif
> > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > new file mode 100644
> > index 0000000000..34634668e5
> > --- /dev/null
> > +++ b/sysdeps/x86_64/isa-default-impl.h
> > @@ -0,0 +1,49 @@
> > +/* Utility for including proper default function based on ISA level
> > + Copyright (C) 2022 Free Software Foundation, Inc.
> > + This file is part of the GNU C Library.
> > +
> > + The GNU C Library is free software; you can redistribute it and/or
> > + modify it under the terms of the GNU Lesser General Public
> > + License as published by the Free Software Foundation; either
> > + version 2.1 of the License, or (at your option) any later version.
> > +
> > + The GNU C Library is distributed in the hope that it will be useful,
> > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + Lesser General Public License for more details.
> > +
> > + You should have received a copy of the GNU Lesser General Public
> > + License along with the GNU C Library; if not, see
> > + <https://www.gnu.org/licenses/>. */
> > +
> > +#include <isa-level.h>
> > +
> > +#ifndef DEFAULT_IMPL_V1
> > +# error "Must have at least ISA V1 Version"
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V2
> > +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V3
> > +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> > +#endif
> > +
> > +#ifndef DEFAULT_IMPL_V4
> > +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> > +#endif
> > +
> > +#if MINIMUM_X86_ISA_LEVEL == 1
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> > +#elif MINIMUM_X86_ISA_LEVEL == 2
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> > +#elif MINIMUM_X86_ISA_LEVEL == 3
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> > +#elif MINIMUM_X86_ISA_LEVEL == 4
> > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> > +#else
> > +# error "Unsupported ISA Level!"
> > +#endif
> > +
> > +#include ISA_DEFAULT_IMPL
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 15:12 ` Noah Goldstein
@ 2022-06-22 15:26 ` H.J. Lu
2022-06-22 15:36 ` Noah Goldstein
0 siblings, 1 reply; 27+ messages in thread
From: H.J. Lu @ 2022-06-22 15:26 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 8:13 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 7:20 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Tue, Jun 21, 2022 at 9:48 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > 1. Factor out some of the ISA level defines in isa-level.c to
> > > standalone header isa-level.h
> > >
> > > 2. Add new headers with ISA level dependent macros for handling
> > > ifuncs.
> > >
> > > Note, this file does not change any code.
> > >
> > > Tested with and without multiarch on x86_64 for ISA levels:
> > > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > > ---
> > > sysdeps/x86/init-arch.h | 4 +-
> > > sysdeps/x86/isa-ifunc-macros.h | 111 ++++++++++++++++++++++++++++++
> > > sysdeps/x86/isa-level.c | 17 ++---
> > > sysdeps/x86/isa-level.h | 99 ++++++++++++++++++++++++++
> > > sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++
> > > 5 files changed, 267 insertions(+), 13 deletions(-)
> > > create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> > > create mode 100644 sysdeps/x86/isa-level.h
> > > create mode 100644 sysdeps/x86_64/isa-default-impl.h
> > >
> > > diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> > > index 277c15f116..a2886a2532 100644
> > > --- a/sysdeps/x86/init-arch.h
> > > +++ b/sysdeps/x86/init-arch.h
> > > @@ -19,7 +19,9 @@
> > > #include <ifunc-init.h>
> > > #include <isa.h>
> > >
> > > -#ifndef __x86_64__
> > > +#ifdef __x86_64__
> > > +# include <isa-ifunc-macros.h>
> > > +#else
> > > /* Due to the reordering and the other nifty extensions in i686, it is
> > > not really good to use heavily i586 optimized code on an i686. It's
> > > better to use i486 code if it isn't an i586. */
> > > diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> > > new file mode 100644
> > > index 0000000000..2aa8fab000
> > > --- /dev/null
> > > +++ b/sysdeps/x86/isa-ifunc-macros.h
> > > @@ -0,0 +1,111 @@
> > > +/* Common ifunc selection utils
> > > + All versions must be listed in ifunc-impl-list.c.
> > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#ifndef _ISA_IFUNC_MACROS_H
> > > +#define _ISA_IFUNC_MACROS_H 1
> > > +
> > > +#include <isa-level.h>
> > > +#include <sys/cdefs.h>
> > > +#include <stdlib.h>
> > > +
> > > +/* Only include at the level of the minimum build ISA or higher. I.e
> > > + if built with ISA=V1, then include all implementations. On the
> > > + other hand if built with ISA=V3 only include V3/V4
> > > + implementations. If there is no implementation at or above the
> > > + minimum build ISA level, then include the highest ISA level
> > > + implementation. */
> > > +#if MINIMUM_X86_ISA_LEVEL <= 4
> > > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> > > +#endif
> > > +#if MINIMUM_X86_ISA_LEVEL <= 3
> > > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> > > +#endif
> > > +#if MINIMUM_X86_ISA_LEVEL <= 2
> > > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> > > +#endif
> > > +#if MINIMUM_X86_ISA_LEVEL <= 1
> > > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> > > +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> > > +#endif
> > > +
> > > +#ifndef return_X86_OPTIMIZE_V4
> > > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > > +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> > > +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> > > +#endif
> > > +#ifndef return_X86_OPTIMIZE_V3
> > > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > > +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> > > +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> > > +#endif
> > > +#ifndef return_X86_OPTIMIZE_V2
> > > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > > +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> > > +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> > > +#endif
> > > +#ifndef return_X86_OPTIMIZE_V1
> > > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > > +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> > > +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> > > +#endif
> > > +
> > > +#if MINIMUM_X86_ISA_LEVEL >= 4
> > > +__errordecl (
> > > + __unreachable_isa_above_4,
> > > + "This code should be unreachable if ISA level >= 4 build ");
> > > +# define X86_ERROR_IF_REACHABLE_V4() __unreachable_isa_above_4 ();
> > > +#else
> > > +# define X86_ERROR_IF_REACHABLE_V4()
> > > +#endif
> > > +
> > > +#if MINIMUM_X86_ISA_LEVEL >= 3
> > > +__errordecl (__unreachable_isa_above_3,
> > > + "This code should be unreachable if ISA level >= 3 build");
> > > +# define X86_ERROR_IF_REACHABLE_V3() __unreachable_isa_above_3 ();
> > > +#else
> > > +# define X86_ERROR_IF_REACHABLE_V3()
> > > +#endif
> > > +
> > > +#if MINIMUM_X86_ISA_LEVEL >= 2
> > > +__errordecl (__unreachable_isa_above_2,
> > > + "This code should be unreachable if ISA level >= 2 build");
> > > +# define X86_ERROR_IF_REACHABLE_V2() __unreachable_isa_above_2 ();
> > > +#else
> > > +# define X86_ERROR_IF_REACHABLE_V2()
> > > +#endif
> >
> > No need for return_X86_OPTIMIZE nor X86_ERROR_IF_REACHABLE.
> > When the minimum ISA level is v3, we will get undefined
> > symbol linker error if compiler doesn't optimize out references
> > to v1 and v2 symbols.
>
> Prefer to keep both.
>
> Think in this case there is a meaningful clarity argument. If build fails
> because undefined reference to sse2 its a less meaningfully error
> than if it fails on the exact attr warning.
We will only see an undefined sse2 symbol error when there
is a mistake. Developers who change IFUNC code should
know why the sse2 symbol isn't optimized out properly. These
2 macros make IFUNC code look very different from others.
> >
> > > +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> > > + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> > > +
> > > +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> > > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > > + || CPU_FEATURE_USABLE_P (ptr, name))
> > > +
> > > +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> > > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > > + || CPU_FEATURES_ARCH_P (ptr, name))
> > > +
> > > +#endif
> > > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > > index 09cd72ab20..5b7a2da870 100644
> > > --- a/sysdeps/x86/isa-level.c
> > > +++ b/sysdeps/x86/isa-level.c
> > > @@ -26,38 +26,31 @@
> > > <https://www.gnu.org/licenses/>. */
> > >
> > > #include <elf.h>
> > > -
> > > +#include <sysdeps/x86/isa-level.h>
> > > /* ELF program property for x86 ISA level. */
> > > #ifdef INCLUDE_X86_ISA_LEVEL
> > > -# if defined __SSE__ && defined __SSE2__
> > > +# if MINIMUM_X86_ISA_LEVEL >= 1
> > > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > > # else
> > > # define ISA_BASELINE 0
> > > # endif
> > >
> > > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > > - && defined __SSE4_2__
> > > +# if MINIMUM_X86_ISA_LEVEL >= 2
> > > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > > # else
> > > # define ISA_V2 0
> > > # endif
> > >
> > > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > > - && defined __BMI__ && defined __BMI2__
> > > +# if MINIMUM_X86_ISA_LEVEL >= 3
> > > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > > # else
> > > # define ISA_V3 0
> > > # endif
> > >
> > > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > > - && defined __AVX512VL__
> > > +# if MINIMUM_X86_ISA_LEVEL >= 4
> > > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > > # else
> > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > new file mode 100644
> > > index 0000000000..21366b3132
> > > --- /dev/null
> > > +++ b/sysdeps/x86/isa-level.h
> > > @@ -0,0 +1,99 @@
> > > +/* Header defining the minimum x86 ISA level
> > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + In addition to the permissions in the GNU Lesser General Public
> > > + License, the Free Software Foundation gives you unlimited
> > > + permission to link the compiled version of this file with other
> > > + programs, and to distribute those programs without any restriction
> > > + coming from the use of this file. (The Lesser General Public
> > > + License restrictions do apply in other respects; for example, they
> > > + cover modification of the file, and distribution when not linked
> > > + into another program.)
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#ifndef _ISA_LEVEL_H
> > > +#define _ISA_LEVEL_H
> > > +
> > > +#if defined __SSE__ && defined __SSE2__
> > > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > > +# define __X86_ISA_V1 1
> > > +#else
> > > +# define __X86_ISA_V1 0
> > > +#endif
> > > +
> > > +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> > > + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> > > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > > +# define __X86_ISA_V2 1
> > > +#else
> > > +# define __X86_ISA_V2 0
> > > +#endif
> > > +
> > > +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > > + && defined __BMI__ && defined __BMI2__
> > > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > > +# define __X86_ISA_V3 1
> > > +#else
> > > +# define __X86_ISA_V3 0
> > > +#endif
> > > +
> > > +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > > + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> > > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > > +# define __X86_ISA_V4 1
> > > +#else
> > > +# define __X86_ISA_V4 0
> > > +#endif
> > > +
> > > +#define MINIMUM_X86_ISA_LEVEL \
> > > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > > +
> > > +
> > > +/*
> > > + * CPU Features that are hard coded as enabled depending on ISA build
> > > + * level.
> > > + * - Values > 0 features are always ENABLED if:
> > > + * Value >= MINIMUM_X86_ISA_LEVEL
> > > + */
> > > +
> > > +
> > > +/* ISA level >= 4 guaranteed includes. */
> > > +#define AVX512VL_X86_ISA_LEVEL 4
> > > +#define AVX512BW_X86_ISA_LEVEL 4
> > > +
> > > +/* ISA level >= 3 guaranteed includes. */
> > > +#define AVX2_X86_ISA_LEVEL 3
> > > +#define BMI2_X86_ISA_LEVEL 3
> > > +
> > > +/*
> > > + * NB: This may not be fully assumable for ISA level >= 3. From
> > > + * looking over the architectures supported in cpu-features.h the
> > > + * following CPUs may have an issue with this being default set:
> > > + * - AMD Excavator
> > > + */
> > > +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> > > +
> > > +/*
> > > + * KNL (the only cpu that sets this supported in cpu-features.h)
> > > + * builds with ISA V1 so this shouldn't harm any architectures.
> > > + */
> > > +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > +
> > > +
> > > +#endif
> > > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > > new file mode 100644
> > > index 0000000000..34634668e5
> > > --- /dev/null
> > > +++ b/sysdeps/x86_64/isa-default-impl.h
> > > @@ -0,0 +1,49 @@
> > > +/* Utility for including proper default function based on ISA level
> > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > + This file is part of the GNU C Library.
> > > +
> > > + The GNU C Library is free software; you can redistribute it and/or
> > > + modify it under the terms of the GNU Lesser General Public
> > > + License as published by the Free Software Foundation; either
> > > + version 2.1 of the License, or (at your option) any later version.
> > > +
> > > + The GNU C Library is distributed in the hope that it will be useful,
> > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > + Lesser General Public License for more details.
> > > +
> > > + You should have received a copy of the GNU Lesser General Public
> > > + License along with the GNU C Library; if not, see
> > > + <https://www.gnu.org/licenses/>. */
> > > +
> > > +#include <isa-level.h>
> > > +
> > > +#ifndef DEFAULT_IMPL_V1
> > > +# error "Must have at least ISA V1 Version"
> > > +#endif
> > > +
> > > +#ifndef DEFAULT_IMPL_V2
> > > +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> > > +#endif
> > > +
> > > +#ifndef DEFAULT_IMPL_V3
> > > +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> > > +#endif
> > > +
> > > +#ifndef DEFAULT_IMPL_V4
> > > +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> > > +#endif
> > > +
> > > +#if MINIMUM_X86_ISA_LEVEL == 1
> > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> > > +#elif MINIMUM_X86_ISA_LEVEL == 2
> > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> > > +#elif MINIMUM_X86_ISA_LEVEL == 3
> > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> > > +#elif MINIMUM_X86_ISA_LEVEL == 4
> > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> > > +#else
> > > +# error "Unsupported ISA Level!"
> > > +#endif
> > > +
> > > +#include ISA_DEFAULT_IMPL
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > H.J.
--
H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 15:26 ` H.J. Lu
@ 2022-06-22 15:36 ` Noah Goldstein
2022-06-22 15:44 ` H.J. Lu
0 siblings, 1 reply; 27+ messages in thread
From: Noah Goldstein @ 2022-06-22 15:36 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 8:27 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 8:13 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > On Wed, Jun 22, 2022 at 7:20 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Tue, Jun 21, 2022 at 9:48 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > >
> > > > 1. Factor out some of the ISA level defines in isa-level.c to
> > > > standalone header isa-level.h
> > > >
> > > > 2. Add new headers with ISA level dependent macros for handling
> > > > ifuncs.
> > > >
> > > > Note, this file does not change any code.
> > > >
> > > > Tested with and without multiarch on x86_64 for ISA levels:
> > > > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > > > ---
> > > > sysdeps/x86/init-arch.h | 4 +-
> > > > sysdeps/x86/isa-ifunc-macros.h | 111 ++++++++++++++++++++++++++++++
> > > > sysdeps/x86/isa-level.c | 17 ++---
> > > > sysdeps/x86/isa-level.h | 99 ++++++++++++++++++++++++++
> > > > sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++
> > > > 5 files changed, 267 insertions(+), 13 deletions(-)
> > > > create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> > > > create mode 100644 sysdeps/x86/isa-level.h
> > > > create mode 100644 sysdeps/x86_64/isa-default-impl.h
> > > >
> > > > diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> > > > index 277c15f116..a2886a2532 100644
> > > > --- a/sysdeps/x86/init-arch.h
> > > > +++ b/sysdeps/x86/init-arch.h
> > > > @@ -19,7 +19,9 @@
> > > > #include <ifunc-init.h>
> > > > #include <isa.h>
> > > >
> > > > -#ifndef __x86_64__
> > > > +#ifdef __x86_64__
> > > > +# include <isa-ifunc-macros.h>
> > > > +#else
> > > > /* Due to the reordering and the other nifty extensions in i686, it is
> > > > not really good to use heavily i586 optimized code on an i686. It's
> > > > better to use i486 code if it isn't an i586. */
> > > > diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> > > > new file mode 100644
> > > > index 0000000000..2aa8fab000
> > > > --- /dev/null
> > > > +++ b/sysdeps/x86/isa-ifunc-macros.h
> > > > @@ -0,0 +1,111 @@
> > > > +/* Common ifunc selection utils
> > > > + All versions must be listed in ifunc-impl-list.c.
> > > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > > + This file is part of the GNU C Library.
> > > > +
> > > > + The GNU C Library is free software; you can redistribute it and/or
> > > > + modify it under the terms of the GNU Lesser General Public
> > > > + License as published by the Free Software Foundation; either
> > > > + version 2.1 of the License, or (at your option) any later version.
> > > > +
> > > > + The GNU C Library is distributed in the hope that it will be useful,
> > > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > > + Lesser General Public License for more details.
> > > > +
> > > > + You should have received a copy of the GNU Lesser General Public
> > > > + License along with the GNU C Library; if not, see
> > > > + <https://www.gnu.org/licenses/>. */
> > > > +
> > > > +#ifndef _ISA_IFUNC_MACROS_H
> > > > +#define _ISA_IFUNC_MACROS_H 1
> > > > +
> > > > +#include <isa-level.h>
> > > > +#include <sys/cdefs.h>
> > > > +#include <stdlib.h>
> > > > +
> > > > +/* Only include at the level of the minimum build ISA or higher. I.e
> > > > + if built with ISA=V1, then include all implementations. On the
> > > > + other hand if built with ISA=V3 only include V3/V4
> > > > + implementations. If there is no implementation at or above the
> > > > + minimum build ISA level, then include the highest ISA level
> > > > + implementation. */
> > > > +#if MINIMUM_X86_ISA_LEVEL <= 4
> > > > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > > +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> > > > +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> > > > +#endif
> > > > +#if MINIMUM_X86_ISA_LEVEL <= 3
> > > > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > > +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> > > > +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> > > > +#endif
> > > > +#if MINIMUM_X86_ISA_LEVEL <= 2
> > > > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > > +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> > > > +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> > > > +#endif
> > > > +#if MINIMUM_X86_ISA_LEVEL <= 1
> > > > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > > +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> > > > +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> > > > +#endif
> > > > +
> > > > +#ifndef return_X86_OPTIMIZE_V4
> > > > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > > > +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> > > > +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> > > > +#endif
> > > > +#ifndef return_X86_OPTIMIZE_V3
> > > > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > > > +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> > > > +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> > > > +#endif
> > > > +#ifndef return_X86_OPTIMIZE_V2
> > > > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > > > +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> > > > +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> > > > +#endif
> > > > +#ifndef return_X86_OPTIMIZE_V1
> > > > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > > > +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> > > > +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> > > > +#endif
> > > > +
> > > > +#if MINIMUM_X86_ISA_LEVEL >= 4
> > > > +__errordecl (
> > > > + __unreachable_isa_above_4,
> > > > + "This code should be unreachable if ISA level >= 4 build ");
> > > > +# define X86_ERROR_IF_REACHABLE_V4() __unreachable_isa_above_4 ();
> > > > +#else
> > > > +# define X86_ERROR_IF_REACHABLE_V4()
> > > > +#endif
> > > > +
> > > > +#if MINIMUM_X86_ISA_LEVEL >= 3
> > > > +__errordecl (__unreachable_isa_above_3,
> > > > + "This code should be unreachable if ISA level >= 3 build");
> > > > +# define X86_ERROR_IF_REACHABLE_V3() __unreachable_isa_above_3 ();
> > > > +#else
> > > > +# define X86_ERROR_IF_REACHABLE_V3()
> > > > +#endif
> > > > +
> > > > +#if MINIMUM_X86_ISA_LEVEL >= 2
> > > > +__errordecl (__unreachable_isa_above_2,
> > > > + "This code should be unreachable if ISA level >= 2 build");
> > > > +# define X86_ERROR_IF_REACHABLE_V2() __unreachable_isa_above_2 ();
> > > > +#else
> > > > +# define X86_ERROR_IF_REACHABLE_V2()
> > > > +#endif
> > >
> > > No need for return_X86_OPTIMIZE nor X86_ERROR_IF_REACHABLE.
> > > When the minimum ISA level is v3, we will get undefined
> > > symbol linker error if compiler doesn't optimize out references
> > > to v1 and v2 symbols.
> >
> > Prefer to keep both.
> >
> > Think in this case there is a meaningful clarity argument. If build fails
> > because undefined reference to sse2 its a less meaningfully error
> > than if it fails on the exact attr warning.
>
> We will only see an undefined sse2 symbol error when there
> is a mistake. Developers who change IFUNC code should
> know why the sse2 symbol isn't optimized out properly. These
> 2 macros make IFUNC code look very different from others.
>
Well yes because this is the first function we are changing, but the
plan to do the same thing in all other functions and this will become
the norm.
> > >
> > > > +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> > > > + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> > > > +
> > > > +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> > > > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > > > + || CPU_FEATURE_USABLE_P (ptr, name))
> > > > +
> > > > +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> > > > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > > > + || CPU_FEATURES_ARCH_P (ptr, name))
> > > > +
> > > > +#endif
> > > > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > > > index 09cd72ab20..5b7a2da870 100644
> > > > --- a/sysdeps/x86/isa-level.c
> > > > +++ b/sysdeps/x86/isa-level.c
> > > > @@ -26,38 +26,31 @@
> > > > <https://www.gnu.org/licenses/>. */
> > > >
> > > > #include <elf.h>
> > > > -
> > > > +#include <sysdeps/x86/isa-level.h>
> > > > /* ELF program property for x86 ISA level. */
> > > > #ifdef INCLUDE_X86_ISA_LEVEL
> > > > -# if defined __SSE__ && defined __SSE2__
> > > > +# if MINIMUM_X86_ISA_LEVEL >= 1
> > > > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > > > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > > > # else
> > > > # define ISA_BASELINE 0
> > > > # endif
> > > >
> > > > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > > > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > > > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > > > - && defined __SSE4_2__
> > > > +# if MINIMUM_X86_ISA_LEVEL >= 2
> > > > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > > > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > > > # else
> > > > # define ISA_V2 0
> > > > # endif
> > > >
> > > > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > > > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > > > - && defined __BMI__ && defined __BMI2__
> > > > +# if MINIMUM_X86_ISA_LEVEL >= 3
> > > > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > > > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > > > # else
> > > > # define ISA_V3 0
> > > > # endif
> > > >
> > > > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > > > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > > > - && defined __AVX512VL__
> > > > +# if MINIMUM_X86_ISA_LEVEL >= 4
> > > > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > > > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > > > # else
> > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > new file mode 100644
> > > > index 0000000000..21366b3132
> > > > --- /dev/null
> > > > +++ b/sysdeps/x86/isa-level.h
> > > > @@ -0,0 +1,99 @@
> > > > +/* Header defining the minimum x86 ISA level
> > > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > > + This file is part of the GNU C Library.
> > > > +
> > > > + The GNU C Library is free software; you can redistribute it and/or
> > > > + modify it under the terms of the GNU Lesser General Public
> > > > + License as published by the Free Software Foundation; either
> > > > + version 2.1 of the License, or (at your option) any later version.
> > > > +
> > > > + In addition to the permissions in the GNU Lesser General Public
> > > > + License, the Free Software Foundation gives you unlimited
> > > > + permission to link the compiled version of this file with other
> > > > + programs, and to distribute those programs without any restriction
> > > > + coming from the use of this file. (The Lesser General Public
> > > > + License restrictions do apply in other respects; for example, they
> > > > + cover modification of the file, and distribution when not linked
> > > > + into another program.)
> > > > +
> > > > + The GNU C Library is distributed in the hope that it will be useful,
> > > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > > + Lesser General Public License for more details.
> > > > +
> > > > + You should have received a copy of the GNU Lesser General Public
> > > > + License along with the GNU C Library; if not, see
> > > > + <https://www.gnu.org/licenses/>. */
> > > > +
> > > > +#ifndef _ISA_LEVEL_H
> > > > +#define _ISA_LEVEL_H
> > > > +
> > > > +#if defined __SSE__ && defined __SSE2__
> > > > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > > > +# define __X86_ISA_V1 1
> > > > +#else
> > > > +# define __X86_ISA_V1 0
> > > > +#endif
> > > > +
> > > > +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > > > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> > > > + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> > > > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > > > +# define __X86_ISA_V2 1
> > > > +#else
> > > > +# define __X86_ISA_V2 0
> > > > +#endif
> > > > +
> > > > +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > > > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > > > + && defined __BMI__ && defined __BMI2__
> > > > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > > > +# define __X86_ISA_V3 1
> > > > +#else
> > > > +# define __X86_ISA_V3 0
> > > > +#endif
> > > > +
> > > > +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > > > + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> > > > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > > > +# define __X86_ISA_V4 1
> > > > +#else
> > > > +# define __X86_ISA_V4 0
> > > > +#endif
> > > > +
> > > > +#define MINIMUM_X86_ISA_LEVEL \
> > > > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > > > +
> > > > +
> > > > +/*
> > > > + * CPU Features that are hard coded as enabled depending on ISA build
> > > > + * level.
> > > > + * - Values > 0 features are always ENABLED if:
> > > > + * Value >= MINIMUM_X86_ISA_LEVEL
> > > > + */
> > > > +
> > > > +
> > > > +/* ISA level >= 4 guaranteed includes. */
> > > > +#define AVX512VL_X86_ISA_LEVEL 4
> > > > +#define AVX512BW_X86_ISA_LEVEL 4
> > > > +
> > > > +/* ISA level >= 3 guaranteed includes. */
> > > > +#define AVX2_X86_ISA_LEVEL 3
> > > > +#define BMI2_X86_ISA_LEVEL 3
> > > > +
> > > > +/*
> > > > + * NB: This may not be fully assumable for ISA level >= 3. From
> > > > + * looking over the architectures supported in cpu-features.h the
> > > > + * following CPUs may have an issue with this being default set:
> > > > + * - AMD Excavator
> > > > + */
> > > > +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> > > > +
> > > > +/*
> > > > + * KNL (the only cpu that sets this supported in cpu-features.h)
> > > > + * builds with ISA V1 so this shouldn't harm any architectures.
> > > > + */
> > > > +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > > +
> > > > +
> > > > +#endif
> > > > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > > > new file mode 100644
> > > > index 0000000000..34634668e5
> > > > --- /dev/null
> > > > +++ b/sysdeps/x86_64/isa-default-impl.h
> > > > @@ -0,0 +1,49 @@
> > > > +/* Utility for including proper default function based on ISA level
> > > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > > + This file is part of the GNU C Library.
> > > > +
> > > > + The GNU C Library is free software; you can redistribute it and/or
> > > > + modify it under the terms of the GNU Lesser General Public
> > > > + License as published by the Free Software Foundation; either
> > > > + version 2.1 of the License, or (at your option) any later version.
> > > > +
> > > > + The GNU C Library is distributed in the hope that it will be useful,
> > > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > > + Lesser General Public License for more details.
> > > > +
> > > > + You should have received a copy of the GNU Lesser General Public
> > > > + License along with the GNU C Library; if not, see
> > > > + <https://www.gnu.org/licenses/>. */
> > > > +
> > > > +#include <isa-level.h>
> > > > +
> > > > +#ifndef DEFAULT_IMPL_V1
> > > > +# error "Must have at least ISA V1 Version"
> > > > +#endif
> > > > +
> > > > +#ifndef DEFAULT_IMPL_V2
> > > > +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> > > > +#endif
> > > > +
> > > > +#ifndef DEFAULT_IMPL_V3
> > > > +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> > > > +#endif
> > > > +
> > > > +#ifndef DEFAULT_IMPL_V4
> > > > +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> > > > +#endif
> > > > +
> > > > +#if MINIMUM_X86_ISA_LEVEL == 1
> > > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> > > > +#elif MINIMUM_X86_ISA_LEVEL == 2
> > > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> > > > +#elif MINIMUM_X86_ISA_LEVEL == 3
> > > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> > > > +#elif MINIMUM_X86_ISA_LEVEL == 4
> > > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> > > > +#else
> > > > +# error "Unsupported ISA Level!"
> > > > +#endif
> > > > +
> > > > +#include ISA_DEFAULT_IMPL
> > > > --
> > > > 2.34.1
> > > >
> > >
> > >
> > > --
> > > H.J.
>
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds
2022-06-22 15:36 ` Noah Goldstein
@ 2022-06-22 15:44 ` H.J. Lu
0 siblings, 0 replies; 27+ messages in thread
From: H.J. Lu @ 2022-06-22 15:44 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 22, 2022 at 8:37 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Wed, Jun 22, 2022 at 8:27 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Wed, Jun 22, 2022 at 8:13 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > On Wed, Jun 22, 2022 at 7:20 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> > > >
> > > > On Tue, Jun 21, 2022 at 9:48 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > > >
> > > > > 1. Factor out some of the ISA level defines in isa-level.c to
> > > > > standalone header isa-level.h
> > > > >
> > > > > 2. Add new headers with ISA level dependent macros for handling
> > > > > ifuncs.
> > > > >
> > > > > Note, this file does not change any code.
> > > > >
> > > > > Tested with and without multiarch on x86_64 for ISA levels:
> > > > > {generic, x86-64-v2, x86-64-v3, x86-64-v4}
> > > > > ---
> > > > > sysdeps/x86/init-arch.h | 4 +-
> > > > > sysdeps/x86/isa-ifunc-macros.h | 111 ++++++++++++++++++++++++++++++
> > > > > sysdeps/x86/isa-level.c | 17 ++---
> > > > > sysdeps/x86/isa-level.h | 99 ++++++++++++++++++++++++++
> > > > > sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++
> > > > > 5 files changed, 267 insertions(+), 13 deletions(-)
> > > > > create mode 100644 sysdeps/x86/isa-ifunc-macros.h
> > > > > create mode 100644 sysdeps/x86/isa-level.h
> > > > > create mode 100644 sysdeps/x86_64/isa-default-impl.h
> > > > >
> > > > > diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h
> > > > > index 277c15f116..a2886a2532 100644
> > > > > --- a/sysdeps/x86/init-arch.h
> > > > > +++ b/sysdeps/x86/init-arch.h
> > > > > @@ -19,7 +19,9 @@
> > > > > #include <ifunc-init.h>
> > > > > #include <isa.h>
> > > > >
> > > > > -#ifndef __x86_64__
> > > > > +#ifdef __x86_64__
> > > > > +# include <isa-ifunc-macros.h>
> > > > > +#else
> > > > > /* Due to the reordering and the other nifty extensions in i686, it is
> > > > > not really good to use heavily i586 optimized code on an i686. It's
> > > > > better to use i486 code if it isn't an i586. */
> > > > > diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h
> > > > > new file mode 100644
> > > > > index 0000000000..2aa8fab000
> > > > > --- /dev/null
> > > > > +++ b/sysdeps/x86/isa-ifunc-macros.h
> > > > > @@ -0,0 +1,111 @@
> > > > > +/* Common ifunc selection utils
> > > > > + All versions must be listed in ifunc-impl-list.c.
> > > > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > > > + This file is part of the GNU C Library.
> > > > > +
> > > > > + The GNU C Library is free software; you can redistribute it and/or
> > > > > + modify it under the terms of the GNU Lesser General Public
> > > > > + License as published by the Free Software Foundation; either
> > > > > + version 2.1 of the License, or (at your option) any later version.
> > > > > +
> > > > > + The GNU C Library is distributed in the hope that it will be useful,
> > > > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > > > + Lesser General Public License for more details.
> > > > > +
> > > > > + You should have received a copy of the GNU Lesser General Public
> > > > > + License along with the GNU C Library; if not, see
> > > > > + <https://www.gnu.org/licenses/>. */
> > > > > +
> > > > > +#ifndef _ISA_IFUNC_MACROS_H
> > > > > +#define _ISA_IFUNC_MACROS_H 1
> > > > > +
> > > > > +#include <isa-level.h>
> > > > > +#include <sys/cdefs.h>
> > > > > +#include <stdlib.h>
> > > > > +
> > > > > +/* Only include at the level of the minimum build ISA or higher. I.e
> > > > > + if built with ISA=V1, then include all implementations. On the
> > > > > + other hand if built with ISA=V3 only include V3/V4
> > > > > + implementations. If there is no implementation at or above the
> > > > > + minimum build ISA level, then include the highest ISA level
> > > > > + implementation. */
> > > > > +#if MINIMUM_X86_ISA_LEVEL <= 4
> > > > > +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > > > +# define return_X86_OPTIMIZE_V4(...) return OPTIMIZE (__VA_ARGS__)
> > > > > +# define return_X86_OPTIMIZE1_V4(...) return OPTIMIZE1 (__VA_ARGS__)
> > > > > +#endif
> > > > > +#if MINIMUM_X86_ISA_LEVEL <= 3
> > > > > +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > > > +# define return_X86_OPTIMIZE_V3(...) return OPTIMIZE (__VA_ARGS__)
> > > > > +# define return_X86_OPTIMIZE1_V3(...) return OPTIMIZE1 (__VA_ARGS__)
> > > > > +#endif
> > > > > +#if MINIMUM_X86_ISA_LEVEL <= 2
> > > > > +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > > > +# define return_X86_OPTIMIZE_V2(...) return OPTIMIZE (__VA_ARGS__)
> > > > > +# define return_X86_OPTIMIZE1_V2(...) return OPTIMIZE1 (__VA_ARGS__)
> > > > > +#endif
> > > > > +#if MINIMUM_X86_ISA_LEVEL <= 1
> > > > > +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__)
> > > > > +# define return_X86_OPTIMIZE_V1(...) return OPTIMIZE (__VA_ARGS__)
> > > > > +# define return_X86_OPTIMIZE1_V1(...) return OPTIMIZE1 (__VA_ARGS__)
> > > > > +#endif
> > > > > +
> > > > > +#ifndef return_X86_OPTIMIZE_V4
> > > > > +# define X86_IFUNC_IMPL_ADD_V4(...)
> > > > > +# define return_X86_OPTIMIZE_V4(...) (void) (0)
> > > > > +# define return_X86_OPTIMIZE1_V4(...) (void) (0)
> > > > > +#endif
> > > > > +#ifndef return_X86_OPTIMIZE_V3
> > > > > +# define X86_IFUNC_IMPL_ADD_V3(...)
> > > > > +# define return_X86_OPTIMIZE_V3(...) (void) (0)
> > > > > +# define return_X86_OPTIMIZE1_V3(...) (void) (0)
> > > > > +#endif
> > > > > +#ifndef return_X86_OPTIMIZE_V2
> > > > > +# define X86_IFUNC_IMPL_ADD_V2(...)
> > > > > +# define return_X86_OPTIMIZE_V2(...) (void) (0)
> > > > > +# define return_X86_OPTIMIZE1_V2(...) (void) (0)
> > > > > +#endif
> > > > > +#ifndef return_X86_OPTIMIZE_V1
> > > > > +# define X86_IFUNC_IMPL_ADD_V1(...)
> > > > > +# define return_X86_OPTIMIZE_V1(...) (void) (0)
> > > > > +# define return_X86_OPTIMIZE1_V1(...) (void) (0)
> > > > > +#endif
> > > > > +
> > > > > +#if MINIMUM_X86_ISA_LEVEL >= 4
> > > > > +__errordecl (
> > > > > + __unreachable_isa_above_4,
> > > > > + "This code should be unreachable if ISA level >= 4 build ");
> > > > > +# define X86_ERROR_IF_REACHABLE_V4() __unreachable_isa_above_4 ();
> > > > > +#else
> > > > > +# define X86_ERROR_IF_REACHABLE_V4()
> > > > > +#endif
> > > > > +
> > > > > +#if MINIMUM_X86_ISA_LEVEL >= 3
> > > > > +__errordecl (__unreachable_isa_above_3,
> > > > > + "This code should be unreachable if ISA level >= 3 build");
> > > > > +# define X86_ERROR_IF_REACHABLE_V3() __unreachable_isa_above_3 ();
> > > > > +#else
> > > > > +# define X86_ERROR_IF_REACHABLE_V3()
> > > > > +#endif
> > > > > +
> > > > > +#if MINIMUM_X86_ISA_LEVEL >= 2
> > > > > +__errordecl (__unreachable_isa_above_2,
> > > > > + "This code should be unreachable if ISA level >= 2 build");
> > > > > +# define X86_ERROR_IF_REACHABLE_V2() __unreachable_isa_above_2 ();
> > > > > +#else
> > > > > +# define X86_ERROR_IF_REACHABLE_V2()
> > > > > +#endif
> > > >
> > > > No need for return_X86_OPTIMIZE nor X86_ERROR_IF_REACHABLE.
> > > > When the minimum ISA level is v3, we will get undefined
> > > > symbol linker error if compiler doesn't optimize out references
> > > > to v1 and v2 symbols.
> > >
> > > Prefer to keep both.
> > >
> > > Think in this case there is a meaningful clarity argument. If build fails
> > > because undefined reference to sse2 its a less meaningfully error
> > > than if it fails on the exact attr warning.
> >
> > We will only see an undefined sse2 symbol error when there
> > is a mistake. Developers who change IFUNC code should
> > know why the sse2 symbol isn't optimized out properly. These
> > 2 macros make IFUNC code look very different from others.
> >
>
> Well yes because this is the first function we are changing, but the
> plan to do the same thing in all other functions and this will become
> the norm.
I meant it looked different from other non-IFUNC codes. The undefined
sse2 linker error from an IFUNC selector is a very clear indication what
went wrong.
> > > >
> > > > > +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \
> > > > > + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL)
> > > > > +
> > > > > +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
> > > > > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > > > > + || CPU_FEATURE_USABLE_P (ptr, name))
> > > > > +
> > > > > +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \
> > > > > + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \
> > > > > + || CPU_FEATURES_ARCH_P (ptr, name))
> > > > > +
> > > > > +#endif
> > > > > diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
> > > > > index 09cd72ab20..5b7a2da870 100644
> > > > > --- a/sysdeps/x86/isa-level.c
> > > > > +++ b/sysdeps/x86/isa-level.c
> > > > > @@ -26,38 +26,31 @@
> > > > > <https://www.gnu.org/licenses/>. */
> > > > >
> > > > > #include <elf.h>
> > > > > -
> > > > > +#include <sysdeps/x86/isa-level.h>
> > > > > /* ELF program property for x86 ISA level. */
> > > > > #ifdef INCLUDE_X86_ISA_LEVEL
> > > > > -# if defined __SSE__ && defined __SSE2__
> > > > > +# if MINIMUM_X86_ISA_LEVEL >= 1
> > > > > /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > > > > # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
> > > > > # else
> > > > > # define ISA_BASELINE 0
> > > > > # endif
> > > > >
> > > > > -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > > > > - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \
> > > > > - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \
> > > > > - && defined __SSE4_2__
> > > > > +# if MINIMUM_X86_ISA_LEVEL >= 2
> > > > > /* NB: ISAs in x86-64 ISA level v2 are used. */
> > > > > # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
> > > > > # else
> > > > > # define ISA_V2 0
> > > > > # endif
> > > > >
> > > > > -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > > > > - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > > > > - && defined __BMI__ && defined __BMI2__
> > > > > +# if MINIMUM_X86_ISA_LEVEL >= 3
> > > > > /* NB: ISAs in x86-64 ISA level v3 are used. */
> > > > > # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
> > > > > # else
> > > > > # define ISA_V3 0
> > > > > # endif
> > > > >
> > > > > -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > > > > - && defined __AVX512CD__ && defined __AVX512DQ__ \
> > > > > - && defined __AVX512VL__
> > > > > +# if MINIMUM_X86_ISA_LEVEL >= 4
> > > > > /* NB: ISAs in x86-64 ISA level v4 are used. */
> > > > > # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
> > > > > # else
> > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > > new file mode 100644
> > > > > index 0000000000..21366b3132
> > > > > --- /dev/null
> > > > > +++ b/sysdeps/x86/isa-level.h
> > > > > @@ -0,0 +1,99 @@
> > > > > +/* Header defining the minimum x86 ISA level
> > > > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > > > + This file is part of the GNU C Library.
> > > > > +
> > > > > + The GNU C Library is free software; you can redistribute it and/or
> > > > > + modify it under the terms of the GNU Lesser General Public
> > > > > + License as published by the Free Software Foundation; either
> > > > > + version 2.1 of the License, or (at your option) any later version.
> > > > > +
> > > > > + In addition to the permissions in the GNU Lesser General Public
> > > > > + License, the Free Software Foundation gives you unlimited
> > > > > + permission to link the compiled version of this file with other
> > > > > + programs, and to distribute those programs without any restriction
> > > > > + coming from the use of this file. (The Lesser General Public
> > > > > + License restrictions do apply in other respects; for example, they
> > > > > + cover modification of the file, and distribution when not linked
> > > > > + into another program.)
> > > > > +
> > > > > + The GNU C Library is distributed in the hope that it will be useful,
> > > > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > > > + Lesser General Public License for more details.
> > > > > +
> > > > > + You should have received a copy of the GNU Lesser General Public
> > > > > + License along with the GNU C Library; if not, see
> > > > > + <https://www.gnu.org/licenses/>. */
> > > > > +
> > > > > +#ifndef _ISA_LEVEL_H
> > > > > +#define _ISA_LEVEL_H
> > > > > +
> > > > > +#if defined __SSE__ && defined __SSE2__
> > > > > +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
> > > > > +# define __X86_ISA_V1 1
> > > > > +#else
> > > > > +# define __X86_ISA_V1 0
> > > > > +#endif
> > > > > +
> > > > > +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
> > > > > + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
> > > > > + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
> > > > > +/* NB: ISAs in x86-64 ISA level v2 are used. */
> > > > > +# define __X86_ISA_V2 1
> > > > > +#else
> > > > > +# define __X86_ISA_V2 0
> > > > > +#endif
> > > > > +
> > > > > +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
> > > > > + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
> > > > > + && defined __BMI__ && defined __BMI2__
> > > > > +/* NB: ISAs in x86-64 ISA level v3 are used. */
> > > > > +# define __X86_ISA_V3 1
> > > > > +#else
> > > > > +# define __X86_ISA_V3 0
> > > > > +#endif
> > > > > +
> > > > > +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
> > > > > + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
> > > > > +/* NB: ISAs in x86-64 ISA level v4 are used. */
> > > > > +# define __X86_ISA_V4 1
> > > > > +#else
> > > > > +# define __X86_ISA_V4 0
> > > > > +#endif
> > > > > +
> > > > > +#define MINIMUM_X86_ISA_LEVEL \
> > > > > + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
> > > > > +
> > > > > +
> > > > > +/*
> > > > > + * CPU Features that are hard coded as enabled depending on ISA build
> > > > > + * level.
> > > > > + * - Values > 0 features are always ENABLED if:
> > > > > + * Value >= MINIMUM_X86_ISA_LEVEL
> > > > > + */
> > > > > +
> > > > > +
> > > > > +/* ISA level >= 4 guaranteed includes. */
> > > > > +#define AVX512VL_X86_ISA_LEVEL 4
> > > > > +#define AVX512BW_X86_ISA_LEVEL 4
> > > > > +
> > > > > +/* ISA level >= 3 guaranteed includes. */
> > > > > +#define AVX2_X86_ISA_LEVEL 3
> > > > > +#define BMI2_X86_ISA_LEVEL 3
> > > > > +
> > > > > +/*
> > > > > + * NB: This may not be fully assumable for ISA level >= 3. From
> > > > > + * looking over the architectures supported in cpu-features.h the
> > > > > + * following CPUs may have an issue with this being default set:
> > > > > + * - AMD Excavator
> > > > > + */
> > > > > +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
> > > > > +
> > > > > +/*
> > > > > + * KNL (the only cpu that sets this supported in cpu-features.h)
> > > > > + * builds with ISA V1 so this shouldn't harm any architectures.
> > > > > + */
> > > > > +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > > > +
> > > > > +
> > > > > +#endif
> > > > > diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h
> > > > > new file mode 100644
> > > > > index 0000000000..34634668e5
> > > > > --- /dev/null
> > > > > +++ b/sysdeps/x86_64/isa-default-impl.h
> > > > > @@ -0,0 +1,49 @@
> > > > > +/* Utility for including proper default function based on ISA level
> > > > > + Copyright (C) 2022 Free Software Foundation, Inc.
> > > > > + This file is part of the GNU C Library.
> > > > > +
> > > > > + The GNU C Library is free software; you can redistribute it and/or
> > > > > + modify it under the terms of the GNU Lesser General Public
> > > > > + License as published by the Free Software Foundation; either
> > > > > + version 2.1 of the License, or (at your option) any later version.
> > > > > +
> > > > > + The GNU C Library is distributed in the hope that it will be useful,
> > > > > + but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > > > + Lesser General Public License for more details.
> > > > > +
> > > > > + You should have received a copy of the GNU Lesser General Public
> > > > > + License along with the GNU C Library; if not, see
> > > > > + <https://www.gnu.org/licenses/>. */
> > > > > +
> > > > > +#include <isa-level.h>
> > > > > +
> > > > > +#ifndef DEFAULT_IMPL_V1
> > > > > +# error "Must have at least ISA V1 Version"
> > > > > +#endif
> > > > > +
> > > > > +#ifndef DEFAULT_IMPL_V2
> > > > > +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1
> > > > > +#endif
> > > > > +
> > > > > +#ifndef DEFAULT_IMPL_V3
> > > > > +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2
> > > > > +#endif
> > > > > +
> > > > > +#ifndef DEFAULT_IMPL_V4
> > > > > +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3
> > > > > +#endif
> > > > > +
> > > > > +#if MINIMUM_X86_ISA_LEVEL == 1
> > > > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1
> > > > > +#elif MINIMUM_X86_ISA_LEVEL == 2
> > > > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2
> > > > > +#elif MINIMUM_X86_ISA_LEVEL == 3
> > > > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3
> > > > > +#elif MINIMUM_X86_ISA_LEVEL == 4
> > > > > +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4
> > > > > +#else
> > > > > +# error "Unsupported ISA Level!"
> > > > > +#endif
> > > > > +
> > > > > +#include ISA_DEFAULT_IMPL
> > > > > --
> > > > > 2.34.1
> > > > >
> > > >
> > > >
> > > > --
> > > > H.J.
> >
> >
> >
> > --
> > H.J.
--
H.J.
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2022-06-22 15:44 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-17 3:50 [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-17 3:50 ` [PATCH v1 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-17 19:13 ` [PATCH v1 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-17 19:30 ` Noah Goldstein
2022-06-17 20:13 ` Noah Goldstein
2022-06-21 21:29 ` Noah Goldstein
2022-06-21 21:29 ` [PATCH v1 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-21 21:44 ` [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-21 21:44 ` [PATCH v3 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-21 21:56 ` [PATCH v3 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 0:30 ` [PATCH v4 " Noah Goldstein
2022-06-22 0:30 ` [PATCH v4 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 1:36 ` [PATCH v4 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 2:05 ` Noah Goldstein
2022-06-22 2:05 ` [PATCH v5 " Noah Goldstein
2022-06-22 2:05 ` [PATCH v5 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 2:08 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds Noah Goldstein
2022-06-22 2:08 ` [PATCH v6 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 2:49 ` [PATCH v6 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 4:47 ` Noah Goldstein
2022-06-22 4:47 ` [PATCH v7 " Noah Goldstein
2022-06-22 4:47 ` [PATCH v7 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Noah Goldstein
2022-06-22 14:19 ` [PATCH v7 1/2] x86: Add defines / utilities for making ISA specific x86 builds H.J. Lu
2022-06-22 15:12 ` Noah Goldstein
2022-06-22 15:26 ` H.J. Lu
2022-06-22 15:36 ` Noah Goldstein
2022-06-22 15:44 ` H.J. Lu
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