From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id BA353385276D for ; Mon, 3 Oct 2022 21:12:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BA353385276D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62a.google.com with SMTP id kg6so9495153ejc.9 for ; Mon, 03 Oct 2022 14:12:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=SJYSJGiu/7g1Xt3euZxCZjihC+/B72+Nvrb7VDfHIYY=; b=KFCGLbJ6ROPhMKcQVv5Voh6J9YGVX1hMMYYy5izZCY3C2iZD3ypZueiL1Msz9afLRf XAqyvB9Q48/XfZ+XNyfj9Vco3Lor7lo46Ixl0zShDpg184hdP0oHGWCElZdklSNAkJ2P lcQh/6X6XjiLCsa4dlseHk81MtpoiJ5kfshp7ZgMh5OmakWhxrtTgTJUHA/rqV39YvI3 FLeoLVcjtM41VE+fISrzCVjJHKGV/5Zk7UBa29Smx2YfGQWb7CEkPqrSexOb6/bKafoS KFSt/HQWpSJ7JfzdFd1aKcjKWmpd9fgZOlBGYFFuQDHjNkkxNly6p0SS15wrdcIVUtYR SnRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=SJYSJGiu/7g1Xt3euZxCZjihC+/B72+Nvrb7VDfHIYY=; b=bLDx3raM8a98EKBEA4Q2OByLnG4RK7+lvQvRQA7FfsAUnUqQ/Lue5q+Jrygj6tDLG3 wEuXgKteAz8R/guBhPFQVRP0/2VMkAuB8rxr+aM82Tlo1Tk9QZFQ6uKfxFEe09nuDE4V OOZ8SOpuv2Em9fepmt5MAS3pD8aF/hoqlgVZBravNJMypkRIgiJMs64sWehCQC7IIPyU 33iSdK+0QVqlysX9ouQEibliMM4vGFaaf7gF7Zdxd6w1cI8k3klzsdfDiKYCHTRC8kP5 e2Z86ziDkODDJrY6+OUWoVu2ylmnlSMoP1jcgeSgLbpXtPiny1eCHAjuoM79kj9Nvm4+ BEDw== X-Gm-Message-State: ACrzQf0uWZCcfuV4b3Mx/qc0cH8cdYZJYQkrz442T92YSEJNy9riJTcl 1ypnr1VWurWPs9gPz7FPYhC9EF8ae/pIPlleQXebSakW4uM= X-Google-Smtp-Source: AMsMyM5QW2+2qIa+esYW0M1UPos6HkDBygwAoRiZptVtpwXk0FEVNBfiZqqGWBPWrdw9hmfoHfE0qspFaex71vxR368= X-Received: by 2002:a17:906:cc4e:b0:77c:b7a:9de6 with SMTP id mm14-20020a170906cc4e00b0077c0b7a9de6mr15928786ejb.531.1664831546531; Mon, 03 Oct 2022 14:12:26 -0700 (PDT) MIME-Version: 1.0 References: <20221003195944.3274548-1-aurelien@aurel32.net> <20221003195944.3274548-7-aurelien@aurel32.net> In-Reply-To: <20221003195944.3274548-7-aurelien@aurel32.net> From: Noah Goldstein Date: Mon, 3 Oct 2022 14:12:14 -0700 Message-ID: Subject: Re: [PATCH v3 6/8] x86-64: Require BMI2 for AVX2 (raw|w)memchr implementations To: Aurelien Jarno Cc: libc-alpha@sourceware.org, "H . J . Lu" , Sunil K Pandey Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Oct 3, 2022 at 12:59 PM Aurelien Jarno wrote: > > The AVX2 memchr, rawmemchr and wmemchr implementations use the 'bzhi' > and 'sarx' instructions, which belongs to the BMI2 CPU feature. > > Fixes: acfd088a1963 ("x86: Optimize memchr-avx2.S") > Partially resolves: BZ #29611 > --- > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > index fec8790c11..7c84963d92 100644 > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > @@ -69,10 +69,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > && CPU_FEATURE_USABLE (BMI2)), > __memchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2)), > __memchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > && CPU_FEATURE_USABLE (RTM)), > __memchr_avx2_rtm) > /* ISA V2 wrapper for SSE2 implementation because the SSE2 > @@ -335,10 +337,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > && CPU_FEATURE_USABLE (BMI2)), > __rawmemchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2)), > __rawmemchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > && CPU_FEATURE_USABLE (RTM)), > __rawmemchr_avx2_rtm) > /* ISA V2 wrapper for SSE2 implementation because the SSE2 > @@ -927,10 +931,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > && CPU_FEATURE_USABLE (BMI2)), > __wmemchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2)), > __wmemchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > && CPU_FEATURE_USABLE (RTM)), > __wmemchr_avx2_rtm) > /* ISA V2 wrapper for SSE2 implementation because the SSE2 > -- > 2.35.1 > LGTM. Reviewed-by: Noah Goldstein