From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by sourceware.org (Postfix) with ESMTPS id 2C6F13860750 for ; Mon, 3 Oct 2022 21:12:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2C6F13860750 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x532.google.com with SMTP id l22so14847126edj.5 for ; Mon, 03 Oct 2022 14:12:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=7Pv4pNNCtJQG+TPMhBrH26i17Naw9lWlPWRPopVPcMM=; b=Ry6/LP5XcGNBttaerKBf1pcZYasvypoqRs/xpjVs14nvUdPnJlquueeVTp90CU3Igc ZHLjsMRPrjBUrOepiOzUKWmsytqNjZ9cScdJAjPGdUlIVY0PkTs+Xk5AGuyPWRhOTRm5 exQ9TGSs3xcpi1VZ1DAkAIGlmQfZvZFeEhAIt6YFOzjarFk1iLhpAMScWPeLKlLRGflx NqLJlCp7Ro1XrDTPCTqpxmqCJO0P9V9ly/wNjO5DgDR2FIffK9EFu8CfUv7Y2wHmsmfN xaFgKWEx4z5qKsFQzyHe1tRd/BLRJAPuIVWIHNDBSPpkGBUPdNjW6niq3Qz9WCKHQbDI 0czg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=7Pv4pNNCtJQG+TPMhBrH26i17Naw9lWlPWRPopVPcMM=; b=rq6BdeH1/oM2tkhEgWj/+ETbC20GCbloJP+7wyd0+mM4U/keCTmGfcLZO7muMI/nI2 X7Etfmjxzn+6vNuH+cxYRWbr3O0tOi1zyNqmvVPvv+nLyVqhTCU9bPxcaoXUKKcQIoeP SqDTdC4kBdclncUE7CpwyDA4R78UZ6KAjev8K2QR/qIk7/QBCWgqDEWBkM0IQntcCzwo cr/AVQo+4CmJJ3U9NQhkk9gdu/vPRjnXwpIAlZYF4ASHbLGaVUpA109s9WhcFWHyLxIK 0K0nrnmmRDrZDE9GOJTrpvWPVOnMmEjpsmN4jzNO9pqxEQyo5rS1SwEDOAOsRPg9sLj4 IItg== X-Gm-Message-State: ACrzQf3W77eA5U+qHU8rR9PQLr09Zg6jRgVtRA99CsS1IUO38zB/SvoZ SjXjdATOgTcXvKCqIqavhLCMHXT/2uSeanKC7tt2byLkK/E= X-Google-Smtp-Source: AMsMyM7sqSSb0m3LjNwdG/zSlIixweE+2SZnxjjQq8FBZzk6NGrcO8oJC1p3OkXaw0/5JY5p9J//e9Rii3SmziDm0uo= X-Received: by 2002:aa7:c60a:0:b0:458:d707:117 with SMTP id h10-20020aa7c60a000000b00458d7070117mr8801122edq.258.1664831555990; Mon, 03 Oct 2022 14:12:35 -0700 (PDT) MIME-Version: 1.0 References: <20221003195944.3274548-1-aurelien@aurel32.net> <20221003195944.3274548-8-aurelien@aurel32.net> In-Reply-To: <20221003195944.3274548-8-aurelien@aurel32.net> From: Noah Goldstein Date: Mon, 3 Oct 2022 14:12:24 -0700 Message-ID: Subject: Re: [PATCH v3 7/8] x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation To: Aurelien Jarno Cc: libc-alpha@sourceware.org, "H . J . Lu" , Sunil K Pandey Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Oct 3, 2022 at 12:59 PM Aurelien Jarno wrote: > > The AVX2 memrchr implementation uses the 'shlxl' instruction, which > belongs to the BMI2 CPU feature and uses the 'lzcnt' instruction, which > belongs to the LZCNT CPU feature. > > Fixes: af5306a735eb ("x86: Optimize memrchr-avx2.S") > Partially resolves: BZ #29611 > --- > sysdeps/x86/isa-level.h | 1 + > sysdeps/x86_64/multiarch/ifunc-avx2.h | 1 + > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 10 ++++++++-- > 3 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > index 3c4480aba7..bbb90f5c5e 100644 > --- a/sysdeps/x86/isa-level.h > +++ b/sysdeps/x86/isa-level.h > @@ -80,6 +80,7 @@ > #define AVX_X86_ISA_LEVEL 3 > #define AVX2_X86_ISA_LEVEL 3 > #define BMI2_X86_ISA_LEVEL 3 > +#define LZCNT_X86_ISA_LEVEL 3 > #define MOVBE_X86_ISA_LEVEL 3 > > /* ISA level >= 2 guaranteed includes. */ > diff --git a/sysdeps/x86_64/multiarch/ifunc-avx2.h b/sysdeps/x86_64/multiarch/ifunc-avx2.h > index a57a9952f3..f1741083fd 100644 > --- a/sysdeps/x86_64/multiarch/ifunc-avx2.h > +++ b/sysdeps/x86_64/multiarch/ifunc-avx2.h > @@ -37,6 +37,7 @@ IFUNC_SELECTOR (void) > > if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2) > && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2) > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, LZCNT) > && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, > AVX_Fast_Unaligned_Load, )) > { > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > index 7c84963d92..ec1c5b55fb 100644 > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > @@ -209,13 +209,19 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > IFUNC_IMPL (i, name, memrchr, > X86_IFUNC_IMPL_ADD_V4 (array, i, memrchr, > (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW)), > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (BMI2) > + && CPU_FEATURE_USABLE (LZCNT)), > __memrchr_evex) > X86_IFUNC_IMPL_ADD_V3 (array, i, memrchr, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > + && CPU_FEATURE_USABLE (LZCNT)), > __memrchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, memrchr, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > + && CPU_FEATURE_USABLE (LZCNT) > && CPU_FEATURE_USABLE (RTM)), > __memrchr_avx2_rtm) > /* ISA V2 wrapper for SSE2 implementation because the SSE2 > -- > 2.35.1 > LGTM. Reviewed-by: Noah Goldstein