From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc2f.google.com (mail-oo1-xc2f.google.com [IPv6:2607:f8b0:4864:20::c2f]) by sourceware.org (Postfix) with ESMTPS id C65313858C2B for ; Thu, 24 Aug 2023 17:07:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C65313858C2B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oo1-xc2f.google.com with SMTP id 006d021491bc7-57128297bd7so96740eaf.0 for ; Thu, 24 Aug 2023 10:07:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692896822; x=1693501622; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=YzOxvzmS2sJ7PavMVxYifBdHk8pV9teyvYZSCE4tGRY=; b=CjEXIXD4n90idKncuL6AQTGVFIviD6LNomP9FmluTETUb4BOYuiDlNCodzVMQ4XHMB JrQQMFfVdvK5usaB4iYrdCLz55brzuqC6M1LpQygexq4z9SB6Y/ZFN8hhfE6gPgaU7d2 pj7gyMaHBFj1rELsjnhKhv4er9rjS22kzYQsn3843V4KdV3z2lvqq4Iu4qFwrzCcato7 BvU/K+aJWfIZMrvNVZbg/CZtiTL3DjxsZ8Y6IE1qzMEPMJt+i6W77GeHW0bxdl5nElbO QnNCbXI7z9S0Vq3TzxNOh3KanFmiF+Kz2DJ4z6nSLqOZ9n+geKhB5dHDFq5WH02G5LaD VBfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692896822; x=1693501622; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YzOxvzmS2sJ7PavMVxYifBdHk8pV9teyvYZSCE4tGRY=; b=XJITTcLRHSdRgSlcUTLBMDX4g3iQkCOgWyxYG3byB7voKbm0zQJvVmoqtLPgkYsbU2 BYeRXgHr91aEXBPWxrV3Jo4o/fxVO0WIv9HDAvTGaFdqD3CDwOC6gVXVuFe2sIZipazN 6GaOps+pPPw6NJnl6VlumxnZJlDS1BIFEqMFmT+KaZt6G26ElSEb0V52T8qX8qfT3YqN oiNOlQhn4JKwNpjb7yu67xbAEYrdHnPgHG2IMsL0PGuus6NK4eht5JVOPk8fh7+faNmi bc6m+YjB/oS8Eq3xwtbT7/c797nqTW///OMYPiR8RAiCvxvOfvlDOlUfolMar1iOdiRv T5Iw== X-Gm-Message-State: AOJu0YzXFw12bTctEfxxD4aMVVlJQfYFgqlFwvGdzQVB612KXh8xgAAS poj6ogH9CAedgo1BjN9DvcjET9CPVrgASjSxjx9PZTDE X-Google-Smtp-Source: AGHT+IHYMoLlUFfH0iX7UOGCwTXReHOFv4iy4I64/OGGFcpcle/1qff9pUIJ4rgAgoYJ/BFRzr94fRRJDLudvXEsrtc= X-Received: by 2002:a4a:91c7:0:b0:56e:4dea:bc5c with SMTP id e7-20020a4a91c7000000b0056e4deabc5cmr2812667ooh.8.1692896821779; Thu, 24 Aug 2023 10:07:01 -0700 (PDT) MIME-Version: 1.0 References: <20230424050329.1501348-1-goldstein.w.n@gmail.com> <20230607181803.4154764-1-goldstein.w.n@gmail.com> In-Reply-To: From: Noah Goldstein Date: Thu, 24 Aug 2023 12:06:48 -0500 Message-ID: Subject: Re: [PATCH v11 1/3] x86: Increase `non_temporal_threshold` to roughly `sizeof_L3 / 4` To: libc-alpha@sourceware.org Cc: hjl.tools@gmail.com, carlos@systemhalted.org, DJ Delorie , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Aug 22, 2023 at 10:11=E2=80=AFAM Noah Goldstein wrote: > > On Mon, Aug 14, 2023 at 6:00=E2=80=AFPM Noah Goldstein wrote: > > > > On Wed, Jun 7, 2023 at 1:18=E2=80=AFPM Noah Goldstein wrote: > > > > > > Current `non_temporal_threshold` set to roughly '3/4 * sizeof_L3 / > > > ncores_per_socket'. This patch updates that value to roughly > > > 'sizeof_L3 / 4` > > > > > > The original value (specifically dividing the `ncores_per_socket`) wa= s > > > done to limit the amount of other threads' data a `memcpy`/`memset` > > > could evict. > > > > > > Dividing by 'ncores_per_socket', however leads to exceedingly low > > > non-temporal thresholds and leads to using non-temporal stores in > > > cases where REP MOVSB is multiple times faster. > > > > > > Furthermore, non-temporal stores are written directly to main memory > > > so using it at a size much smaller than L3 can place soon to be > > > accessed data much further away than it otherwise could be. As well, > > > modern machines are able to detect streaming patterns (especially if > > > REP MOVSB is used) and provide LRU hints to the memory subsystem. Thi= s > > > in affect caps the total amount of eviction at 1/cache_associativity, > > > far below meaningfully thrashing the entire cache. > > > > > > As best I can tell, the benchmarks that lead this small threshold > > > where done comparing non-temporal stores versus standard cacheable > > > stores. A better comparison (linked below) is to be REP MOVSB which, > > > on the measure systems, is nearly 2x faster than non-temporal stores > > > at the low-end of the previous threshold, and within 10% for over > > > 100MB copies (well past even the current threshold). In cases with a > > > low number of threads competing for bandwidth, REP MOVSB is ~2x faste= r > > > up to `sizeof_L3`. > > > > > > The divisor of `4` is a somewhat arbitrary value. From benchmarks it > > > seems Skylake and Icelake both prefer a divisor of `2`, but older CPU= s > > > such as Broadwell prefer something closer to `8`. This patch is meant > > > to be followed up by another one to make the divisor cpu-specific, bu= t > > > in the meantime (and for easier backporting), this patch settles on > > > `4` as a middle-ground. > > > > > > Benchmarks comparing non-temporal stores, REP MOVSB, and cacheable > > > stores where done using: > > > https://github.com/goldsteinn/memcpy-nt-benchmarks > > > > > > Sheets results (also available in pdf on the github): > > > https://docs.google.com/spreadsheets/d/e/2PACX-1vS183r0rW_jRX6tG_E90m= 9qVuFiMbRIJvi5VAE8yYOvEOIEEc3aSNuEsrFbuXw5c3nGboxMmrupZD7K/pubhtml > > > Reviewed-by: DJ Delorie > > > Reviewed-by: Carlos O'Donell > > > --- > > > sysdeps/x86/dl-cacheinfo.h | 70 +++++++++++++++++++++++-------------= -- > > > 1 file changed, 43 insertions(+), 27 deletions(-) > > > > > > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > > > index 877e73d700..3bd3b3ec1b 100644 > > > --- a/sysdeps/x86/dl-cacheinfo.h > > > +++ b/sysdeps/x86/dl-cacheinfo.h > > > @@ -407,7 +407,7 @@ handle_zhaoxin (int name) > > > } > > > > > > static void > > > -get_common_cache_info (long int *shared_ptr, unsigned int *threads_p= tr, > > > +get_common_cache_info (long int *shared_ptr, long int * shared_per_t= hread_ptr, unsigned int *threads_ptr, > > > long int core) > > > { > > > unsigned int eax; > > > @@ -426,6 +426,7 @@ get_common_cache_info (long int *shared_ptr, unsi= gned int *threads_ptr, > > > unsigned int family =3D cpu_features->basic.family; > > > unsigned int model =3D cpu_features->basic.model; > > > long int shared =3D *shared_ptr; > > > + long int shared_per_thread =3D *shared_per_thread_ptr; > > > unsigned int threads =3D *threads_ptr; > > > bool inclusive_cache =3D true; > > > bool support_count_mask =3D true; > > > @@ -441,6 +442,7 @@ get_common_cache_info (long int *shared_ptr, unsi= gned int *threads_ptr, > > > /* Try L2 otherwise. */ > > > level =3D 2; > > > shared =3D core; > > > + shared_per_thread =3D core; > > > threads_l2 =3D 0; > > > threads_l3 =3D -1; > > > } > > > @@ -597,29 +599,28 @@ get_common_cache_info (long int *shared_ptr, un= signed int *threads_ptr, > > > } > > > else > > > { > > > -intel_bug_no_cache_info: > > > - /* Assume that all logical threads share the highest cache > > > - level. */ > > > - threads > > > - =3D ((cpu_features->features[CPUID_INDEX_1].cpuid.ebx >>= 16) > > > - & 0xff); > > > - } > > > - > > > - /* Cap usage of highest cache level to the number of support= ed > > > - threads. */ > > > - if (shared > 0 && threads > 0) > > > - shared /=3D threads; > > > + intel_bug_no_cache_info: > > > + /* Assume that all logical threads share the highest cache > > > + level. */ > > > + threads =3D ((cpu_features->features[CPUID_INDEX_1].cpuid.e= bx >> 16) > > > + & 0xff); > > > + > > > + /* Get per-thread size of highest level cache. */ > > > + if (shared_per_thread > 0 && threads > 0) > > > + shared_per_thread /=3D threads; > > > + } > > > } > > > > > > /* Account for non-inclusive L2 and L3 caches. */ > > > if (!inclusive_cache) > > > { > > > if (threads_l2 > 0) > > > - core /=3D threads_l2; > > > + shared_per_thread +=3D core / threads_l2; > > > shared +=3D core; > > > } > > > > > > *shared_ptr =3D shared; > > > + *shared_per_thread_ptr =3D shared_per_thread; > > > *threads_ptr =3D threads; > > > } > > > > > > @@ -629,6 +630,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_featu= res) > > > /* Find out what brand of processor. */ > > > long int data =3D -1; > > > long int shared =3D -1; > > > + long int shared_per_thread =3D -1; > > > long int core =3D -1; > > > unsigned int threads =3D 0; > > > unsigned long int level1_icache_size =3D -1; > > > @@ -649,6 +651,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_featu= res) > > > data =3D handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); > > > core =3D handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); > > > shared =3D handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); > > > + shared_per_thread =3D shared; > > > > > > level1_icache_size > > > =3D handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); > > > @@ -672,13 +675,14 @@ dl_init_cacheinfo (struct cpu_features *cpu_fea= tures) > > > level4_cache_size > > > =3D handle_intel (_SC_LEVEL4_CACHE_SIZE, cpu_features); > > > > > > - get_common_cache_info (&shared, &threads, core); > > > + get_common_cache_info (&shared, &shared_per_thread, &threads, = core); > > > } > > > else if (cpu_features->basic.kind =3D=3D arch_kind_zhaoxin) > > > { > > > data =3D handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); > > > core =3D handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); > > > shared =3D handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); > > > + shared_per_thread =3D shared; > > > > > > level1_icache_size =3D handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE)= ; > > > level1_icache_linesize =3D handle_zhaoxin (_SC_LEVEL1_ICACHE_L= INESIZE); > > > @@ -692,13 +696,14 @@ dl_init_cacheinfo (struct cpu_features *cpu_fea= tures) > > > level3_cache_assoc =3D handle_zhaoxin (_SC_LEVEL3_CACHE_ASSOC)= ; > > > level3_cache_linesize =3D handle_zhaoxin (_SC_LEVEL3_CACHE_LIN= ESIZE); > > > > > > - get_common_cache_info (&shared, &threads, core); > > > + get_common_cache_info (&shared, &shared_per_thread, &threads, = core); > > > } > > > else if (cpu_features->basic.kind =3D=3D arch_kind_amd) > > > { > > > data =3D handle_amd (_SC_LEVEL1_DCACHE_SIZE); > > > core =3D handle_amd (_SC_LEVEL2_CACHE_SIZE); > > > shared =3D handle_amd (_SC_LEVEL3_CACHE_SIZE); > > > + shared_per_thread =3D shared; > > > > > > level1_icache_size =3D handle_amd (_SC_LEVEL1_ICACHE_SIZE); > > > level1_icache_linesize =3D handle_amd (_SC_LEVEL1_ICACHE_LINES= IZE); > > > @@ -715,6 +720,9 @@ dl_init_cacheinfo (struct cpu_features *cpu_featu= res) > > > if (shared <=3D 0) > > > /* No shared L3 cache. All we have is the L2 cache. */ > > > shared =3D core; > > > + > > > + if (shared_per_thread <=3D 0) > > > + shared_per_thread =3D shared; > > > } > > > > > > cpu_features->level1_icache_size =3D level1_icache_size; > > > @@ -730,17 +738,25 @@ dl_init_cacheinfo (struct cpu_features *cpu_fea= tures) > > > cpu_features->level3_cache_linesize =3D level3_cache_linesize; > > > cpu_features->level4_cache_size =3D level4_cache_size; > > > > > > - /* The default setting for the non_temporal threshold is 3/4 of on= e > > > - thread's share of the chip's cache. For most Intel and AMD proc= essors > > > - with an initial release date between 2017 and 2020, a thread's = typical > > > - share of the cache is from 500 KBytes to 2 MBytes. Using the 3/= 4 > > > - threshold leaves 125 KBytes to 500 KBytes of the thread's data > > > - in cache after a maximum temporal copy, which will maintain > > > - in cache a reasonable portion of the thread's stack and other > > > - active data. If the threshold is set higher than one thread's > > > - share of the cache, it has a substantial risk of negatively > > > - impacting the performance of other threads running on the chip.= */ > > > - unsigned long int non_temporal_threshold =3D shared * 3 / 4; > > > + /* The default setting for the non_temporal threshold is 1/4 of si= ze > > > + of the chip's cache. For most Intel and AMD processors with an > > > + initial release date between 2017 and 2023, a thread's typical > > > + share of the cache is from 18-64MB. Using the 1/4 L3 is meant t= o > > > + estimate the point where non-temporal stores begin out-competin= g > > > + REP MOVSB. As well the point where the fact that non-temporal > > > + stores are forced back to main memory would already occurred to= the > > > + majority of the lines in the copy. Note, concerns about the > > > + entire L3 cache being evicted by the copy are mostly alleviated > > > + by the fact that modern HW detects streaming patterns and > > > + provides proper LRU hints so that the maximum thrashing > > > + capped at 1/associativity. */ > > > + unsigned long int non_temporal_threshold =3D shared / 4; > > > + /* If no ERMS, we use the per-thread L3 chunking. Normal cacheable= stores run > > > + a higher risk of actually thrashing the cache as they don't hav= e a HW LRU > > > + hint. As well, their performance in highly parallel situations = is > > > + noticeably worse. */ > > > + if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)) > > > + non_temporal_threshold =3D shared_per_thread * 3 / 4; > > > /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts t= he value of > > > 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and = it is best > > > if that operation cannot overflow. Minimum of 0x4040 (16448) be= cause the > > > -- > > > 2.34.1 > > > > > > > Hi All, > > > > I want to backport this series (minus CPUID codes) too 2.28 - 2.37 > > > > The patches I want to backport are: > > > > 1/4 > > ``` > > commit af992e7abdc9049714da76cae1e5e18bc4838fb8 > > Author: Noah Goldstein > > Date: Wed Jun 7 13:18:01 2023 -0500 > > > > x86: Increase `non_temporal_threshold` to roughly `sizeof_L3 / 4` > > ``` > > > > 2/4 > > ``` > > commit 47f747217811db35854ea06741be3685e8bbd44d > > Author: Noah Goldstein > > Date: Mon Jul 17 23:14:33 2023 -0500 > > > > x86: Fix slight bug in `shared_per_thread` cache size calculation. > > ``` > > > > 3/4 > > ``` > > commit 8b9a0af8ca012217bf90d1dc0694f85b49ae09da > > Author: Noah Goldstein > > Date: Tue Jul 18 10:27:59 2023 -0500 > > > > [PATCH v1] x86: Use `3/4*sizeof(per-thread-L3)` as low bound for > > NT threshold. > > ``` > > > > 4/4 > > ``` > > commit 084fb31bc2c5f95ae0b9e6df4d3cf0ff43471ede (origin/master, > > origin/HEAD, master) > > Author: Noah Goldstein > > Date: Thu Aug 10 19:28:24 2023 -0500 > > > > x86: Fix incorrect scope of setting `shared_per_thread` [BZ# 30745] > > ``` > > > > The proposed patches are at: > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 28 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 29 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 30 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 31 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 32 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 33 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 34 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 35 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 36 > > https://gitlab.com/x86-glibc/glibc/-/commits/users/goldsteinn/backport-= 37 > > > > I know the protocol is not to normally backport optimizations, but I'd = argue > > these are closer to bug fixes for a severe misconfiguration than a prop= er > > optimization series. As well, the risk of introducing a correctness re= lated > > bug is exceedingly low. > > > > Typically the type of optimization patch this is discouraged are the on= es > > that actually change a particular function. I.e if these fixes where di= rectly > > to the memmove implementation. These patches, however, don't touch > > any of the memmove code itself, and are just re-tuning a value used by > > memmove which seems categorically different. > > > > The value also only informs memmove strategy. If these patches turn > > out to be deeply buggy and set the new threshold incorrectly, the > > blowback is limited to a bad performance (which we already have), > > and is extremely unlikely to affect correctness in any way. > > > > Thoughts? > > Ping/Any Objections to me backporting? I am going to take the continued lack of objections to mean no one has issue with me backporting these. I will start backporting next week. Will do so piecemeal to give time for issues to emerge before fulling committing.