From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1131.google.com (mail-yw1-x1131.google.com [IPv6:2607:f8b0:4864:20::1131]) by sourceware.org (Postfix) with ESMTPS id A8E2C3841443 for ; Wed, 29 Jun 2022 20:43:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A8E2C3841443 Received: by mail-yw1-x1131.google.com with SMTP id 00721157ae682-31bf3656517so69401327b3.12 for ; Wed, 29 Jun 2022 13:43:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gHfFppTtiVGz7mCTNTF0MQoKMu+L7VKM3JuDdTFwpN4=; b=ib9GyGDK4cyv8t4JXZEGLCEoin4kcU2W4Ird0LGO5H4Vef7g6x+5hUarV+HxWY/4T4 dz7c1wTRPzwuR1Cx0aMdwHj+8Mn/XcF/2NuIFJEiLApcj0fVlSXE1gl/1ylaqueIMY+w W3AInJDSAJhUDBs2m5BlQW8Crn7Kzh7ykw3cH2SHCRI4M7JkEcj1L3fXw5obdCv74TUF +KA7h0+uYLNMietiExnpzLUEHRZoCbnm2VujFgB0HNurrq/dHfaWfB3n1qGgm5nX1Ss+ lVGORk2b6dQU7o8XR3IAHpgu807omUKs4DPB3J6BOAptrJgGD/4cHL/Jewucwh6q0Bqw y57A== X-Gm-Message-State: AJIora/tbepWXCX8NxAVUMhp/ltZwxLC8N54PUciyGs/wrnuHVWT+koH QkbgN82kzEEBqSYlHXWU3A0B3cyUwjIK6Ig0kyjCrE7P+W0= X-Google-Smtp-Source: AGRyM1vhpfRNyga5HK8C5U6MQTBD3SaJCgWZ5znXBCWdU9L25kTE5wqWg+aw7StQTwf5DrYj9Sih1I1XRUTJ+jOtwhs= X-Received: by 2002:a81:415:0:b0:317:7938:e2b1 with SMTP id 21-20020a810415000000b003177938e2b1mr6568739ywe.444.1656535382012; Wed, 29 Jun 2022 13:43:02 -0700 (PDT) MIME-Version: 1.0 References: <20220629202223.293961-1-goldstein.w.n@gmail.com> In-Reply-To: From: Noah Goldstein Date: Wed, 29 Jun 2022 13:42:51 -0700 Message-ID: Subject: Re: [PATCH v2] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments To: "H.J. Lu" Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Jun 2022 20:43:04 -0000 On Wed, Jun 29, 2022 at 1:27 PM H.J. Lu wrote: > > On Wed, Jun 29, 2022 at 1:22 PM Noah Goldstein wrote: > > > > From: "H.J. Lu" > > > > Properly indent X86_IFUNC_IMPL_ADD_VN arguments for memchr, rawmemchr > > and wmemchr. > > > > Co-authored-by: H.J. Lu > > --- > > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 99 +++++++++++----------- > > 1 file changed, 51 insertions(+), 48 deletions(-) > > > > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > > index 1452b2809e..119f5f040b 100644 > > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c > > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > > @@ -58,26 +58,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > > /* Support sysdeps/x86_64/multiarch/memchr.c. */ > > IFUNC_IMPL (i, name, memchr, > > X86_IFUNC_IMPL_ADD_V4 (array, i, memchr, > > - (CPU_FEATURE_USABLE (AVX512VL) > > - && CPU_FEATURE_USABLE (AVX512BW) > > - && CPU_FEATURE_USABLE (BMI2)), > > - __memchr_evex) > > + (CPU_FEATURE_USABLE (AVX512VL) > > + && CPU_FEATURE_USABLE (AVX512BW) > > + && CPU_FEATURE_USABLE (BMI2)), > > + __memchr_evex) > > X86_IFUNC_IMPL_ADD_V4 (array, i, memchr, > > - (CPU_FEATURE_USABLE (AVX512VL) > > - && CPU_FEATURE_USABLE (AVX512BW) > > - && CPU_FEATURE_USABLE (BMI2)), > > - __memchr_evex_rtm) > > + (CPU_FEATURE_USABLE (AVX512VL) > > + && CPU_FEATURE_USABLE (AVX512BW) > > + && CPU_FEATURE_USABLE (BMI2)), > > + __memchr_evex_rtm) > > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, > > - CPU_FEATURE_USABLE (AVX2), > > - __memchr_avx2) > > + CPU_FEATURE_USABLE (AVX2), > > + __memchr_avx2) > > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, > > - (CPU_FEATURE_USABLE (AVX2) > > - && CPU_FEATURE_USABLE (RTM)), > > - __memchr_avx2_rtm) > > - /* Can be lowered to V1 if a V2 implementation is added. */ > > + (CPU_FEATURE_USABLE (AVX2) > > + && CPU_FEATURE_USABLE (RTM)), > > + __memchr_avx2_rtm) > > + /* ISA V2 wrapper for sse2 implementation because the sse2 > > It should be SSE2, not sse2. Fixed in V3. > > > + implementation is also used at ISA level 2. */ > > X86_IFUNC_IMPL_ADD_V2 (array, i, memchr, > > - 1, > > - __memchr_sse2)) > > + 1, > > + __memchr_sse2)) > > > > /* Support sysdeps/x86_64/multiarch/memcmp.c. */ > > IFUNC_IMPL (i, name, memcmp, > > @@ -315,26 +316,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > > /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */ > > IFUNC_IMPL (i, name, rawmemchr, > > X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr, > > - (CPU_FEATURE_USABLE (AVX512VL) > > - && CPU_FEATURE_USABLE (AVX512BW) > > - && CPU_FEATURE_USABLE (BMI2)), > > - __rawmemchr_evex) > > + (CPU_FEATURE_USABLE (AVX512VL) > > + && CPU_FEATURE_USABLE (AVX512BW) > > + && CPU_FEATURE_USABLE (BMI2)), > > + __rawmemchr_evex) > > X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr, > > - (CPU_FEATURE_USABLE (AVX512VL) > > - && CPU_FEATURE_USABLE (AVX512BW) > > - && CPU_FEATURE_USABLE (BMI2)), > > - __rawmemchr_evex_rtm) > > + (CPU_FEATURE_USABLE (AVX512VL) > > + && CPU_FEATURE_USABLE (AVX512BW) > > + && CPU_FEATURE_USABLE (BMI2)), > > + __rawmemchr_evex_rtm) > > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, > > - CPU_FEATURE_USABLE (AVX2), > > - __rawmemchr_avx2) > > + CPU_FEATURE_USABLE (AVX2), > > + __rawmemchr_avx2) > > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, > > - (CPU_FEATURE_USABLE (AVX2) > > - && CPU_FEATURE_USABLE (RTM)), > > - __rawmemchr_avx2_rtm) > > - /* Can be lowered to V1 if a V2 implementation is added. */ > > + (CPU_FEATURE_USABLE (AVX2) > > + && CPU_FEATURE_USABLE (RTM)), > > + __rawmemchr_avx2_rtm) > > + /* ISA V2 wrapper for sse2 implementation because the sse2 > > + implementation is also used at ISA level 2. */ > > X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr, > > - 1, > > - __rawmemchr_sse2)) > > + 1, > > + __rawmemchr_sse2)) > > > > /* Support sysdeps/x86_64/multiarch/strlen.c. */ > > IFUNC_IMPL (i, name, strlen, > > @@ -784,26 +786,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > > /* Support sysdeps/x86_64/multiarch/wmemchr.c. */ > > IFUNC_IMPL (i, name, wmemchr, > > X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr, > > - (CPU_FEATURE_USABLE (AVX512VL) > > - && CPU_FEATURE_USABLE (AVX512BW) > > - && CPU_FEATURE_USABLE (BMI2)), > > - __wmemchr_evex) > > + (CPU_FEATURE_USABLE (AVX512VL) > > + && CPU_FEATURE_USABLE (AVX512BW) > > + && CPU_FEATURE_USABLE (BMI2)), > > + __wmemchr_evex) > > X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr, > > - (CPU_FEATURE_USABLE (AVX512VL) > > - && CPU_FEATURE_USABLE (AVX512BW) > > - && CPU_FEATURE_USABLE (BMI2)), > > - __wmemchr_evex_rtm) > > + (CPU_FEATURE_USABLE (AVX512VL) > > + && CPU_FEATURE_USABLE (AVX512BW) > > + && CPU_FEATURE_USABLE (BMI2)), > > + __wmemchr_evex_rtm) > > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, > > - CPU_FEATURE_USABLE (AVX2), > > - __wmemchr_avx2) > > + CPU_FEATURE_USABLE (AVX2), > > + __wmemchr_avx2) > > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, > > - (CPU_FEATURE_USABLE (AVX2) > > - && CPU_FEATURE_USABLE (RTM)), > > - __wmemchr_avx2_rtm) > > - /* Can be lowered to V1 if a V2 implementation is added. */ > > + (CPU_FEATURE_USABLE (AVX2) > > + && CPU_FEATURE_USABLE (RTM)), > > + __wmemchr_avx2_rtm) > > + /* ISA V2 wrapper for sse2 implementation because the sse2 > > + implementation is also used at ISA level 2. */ > > X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr, > > - 1, > > - __wmemchr_sse2)) > > + 1, > > + __wmemchr_sse2)) > > > > /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */ > > IFUNC_IMPL (i, name, wmemcmp, > > -- > > 2.34.1 > > > > > -- > H.J.