* [PATCH v1] x86: Add more feature definitions to isa-level.h
@ 2022-06-28 1:04 Noah Goldstein
2022-06-28 1:56 ` H.J. Lu
` (4 more replies)
0 siblings, 5 replies; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 1:04 UTC (permalink / raw)
To: libc-alpha
This commit doesn't change anything in itself. It is just to add
definitions that will be needed by future patches.
---
sysdeps/x86/isa-level.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
index f293aea906..f5ca625c21 100644
--- a/sysdeps/x86/isa-level.h
+++ b/sysdeps/x86/isa-level.h
@@ -71,11 +71,13 @@
#define AVX512F_X86_ISA_LEVEL 4
#define AVX512VL_X86_ISA_LEVEL 4
#define AVX512BW_X86_ISA_LEVEL 4
+#define AVX512DQ_X86_ISA_LEVEL 4
/* ISA level >= 3 guaranteed includes. */
#define AVX_X86_ISA_LEVEL 3
#define AVX2_X86_ISA_LEVEL 3
#define BMI2_X86_ISA_LEVEL 3
+#define MOVBE_X86_ISA_LEVEL 3
/* NB: This feature is enabled when ISA level >= 3, which was disabled
for the following CPUs:
@@ -89,6 +91,11 @@
when ISA level < 3. */
#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+/* ISA level >= 2 guaranteed includes. */
+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
+#define SSE4_2_X86_ISA_LEVEL 2
+#define SSSE3_X86_ISA_LEVEL 2
+
/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
runtime checks. They differ in two ways.
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1] x86: Add more feature definitions to isa-level.h
2022-06-28 1:04 [PATCH v1] x86: Add more feature definitions to isa-level.h Noah Goldstein
@ 2022-06-28 1:56 ` H.J. Lu
2022-06-28 2:04 ` Noah Goldstein
2022-06-28 2:03 ` [PATCH v2] " Noah Goldstein
` (3 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 1:56 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 6:05 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> This commit doesn't change anything in itself. It is just to add
> definitions that will be needed by future patches.
> ---
> sysdeps/x86/isa-level.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> index f293aea906..f5ca625c21 100644
> --- a/sysdeps/x86/isa-level.h
> +++ b/sysdeps/x86/isa-level.h
> @@ -71,11 +71,13 @@
> #define AVX512F_X86_ISA_LEVEL 4
> #define AVX512VL_X86_ISA_LEVEL 4
> #define AVX512BW_X86_ISA_LEVEL 4
> +#define AVX512DQ_X86_ISA_LEVEL 4
>
> /* ISA level >= 3 guaranteed includes. */
> #define AVX_X86_ISA_LEVEL 3
> #define AVX2_X86_ISA_LEVEL 3
> #define BMI2_X86_ISA_LEVEL 3
> +#define MOVBE_X86_ISA_LEVEL 3
>
> /* NB: This feature is enabled when ISA level >= 3, which was disabled
> for the following CPUs:
> @@ -89,6 +91,11 @@
> when ISA level < 3. */
> #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
>
> +/* ISA level >= 2 guaranteed includes. */
> +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
This should be defined as enabled/disabled, similarly to
AVX_Fast_Unaligned_Load_X86_ISA_LEVEL.
> +#define SSE4_2_X86_ISA_LEVEL 2
> +#define SSSE3_X86_ISA_LEVEL 2
> +
> /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> runtime checks. They differ in two ways.
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2] x86: Add more feature definitions to isa-level.h
2022-06-28 1:04 [PATCH v1] x86: Add more feature definitions to isa-level.h Noah Goldstein
2022-06-28 1:56 ` H.J. Lu
@ 2022-06-28 2:03 ` Noah Goldstein
2022-06-28 2:29 ` H.J. Lu
2022-06-28 3:26 ` [PATCH v3] " Noah Goldstein
` (2 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 2:03 UTC (permalink / raw)
To: libc-alpha
This commit doesn't change anything in itself. It is just to add
definitions that will be needed by future patches.
---
sysdeps/x86/isa-level.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
index f293aea906..024d1deb80 100644
--- a/sysdeps/x86/isa-level.h
+++ b/sysdeps/x86/isa-level.h
@@ -71,11 +71,13 @@
#define AVX512F_X86_ISA_LEVEL 4
#define AVX512VL_X86_ISA_LEVEL 4
#define AVX512BW_X86_ISA_LEVEL 4
+#define AVX512DQ_X86_ISA_LEVEL 4
/* ISA level >= 3 guaranteed includes. */
#define AVX_X86_ISA_LEVEL 3
#define AVX2_X86_ISA_LEVEL 3
#define BMI2_X86_ISA_LEVEL 3
+#define MOVBE_X86_ISA_LEVEL 3
/* NB: This feature is enabled when ISA level >= 3, which was disabled
for the following CPUs:
@@ -89,6 +91,14 @@
when ISA level < 3. */
#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+/* ISA level >= 2 guaranteed includes. */
+#define SSE4_2_X86_ISA_LEVEL 2
+#define SSSE3_X86_ISA_LEVEL 2
+
+/* NB: This feature is enabled when ISA level >= 2. No CPUs should be
+ affected by this. */
+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
+
/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
runtime checks. They differ in two ways.
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1] x86: Add more feature definitions to isa-level.h
2022-06-28 1:56 ` H.J. Lu
@ 2022-06-28 2:04 ` Noah Goldstein
0 siblings, 0 replies; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 2:04 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 6:57 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 6:05 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > This commit doesn't change anything in itself. It is just to add
> > definitions that will be needed by future patches.
> > ---
> > sysdeps/x86/isa-level.h | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > index f293aea906..f5ca625c21 100644
> > --- a/sysdeps/x86/isa-level.h
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -71,11 +71,13 @@
> > #define AVX512F_X86_ISA_LEVEL 4
> > #define AVX512VL_X86_ISA_LEVEL 4
> > #define AVX512BW_X86_ISA_LEVEL 4
> > +#define AVX512DQ_X86_ISA_LEVEL 4
> >
> > /* ISA level >= 3 guaranteed includes. */
> > #define AVX_X86_ISA_LEVEL 3
> > #define AVX2_X86_ISA_LEVEL 3
> > #define BMI2_X86_ISA_LEVEL 3
> > +#define MOVBE_X86_ISA_LEVEL 3
> >
> > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > for the following CPUs:
> > @@ -89,6 +91,11 @@
> > when ISA level < 3. */
> > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> >
> > +/* ISA level >= 2 guaranteed includes. */
> > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
>
> This should be defined as enabled/disabled, similarly to
> AVX_Fast_Unaligned_Load_X86_ISA_LEVEL.
Added a comment in the same vein as AVX_Fast_...
I don't think this overrides the natural choice of any CPU
so essentially said as much.
>
> > +#define SSE4_2_X86_ISA_LEVEL 2
> > +#define SSSE3_X86_ISA_LEVEL 2
> > +
> > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > runtime checks. They differ in two ways.
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2] x86: Add more feature definitions to isa-level.h
2022-06-28 2:03 ` [PATCH v2] " Noah Goldstein
@ 2022-06-28 2:29 ` H.J. Lu
2022-06-28 2:34 ` Noah Goldstein
0 siblings, 1 reply; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 2:29 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> This commit doesn't change anything in itself. It is just to add
> definitions that will be needed by future patches.
> ---
> sysdeps/x86/isa-level.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> index f293aea906..024d1deb80 100644
> --- a/sysdeps/x86/isa-level.h
> +++ b/sysdeps/x86/isa-level.h
> @@ -71,11 +71,13 @@
> #define AVX512F_X86_ISA_LEVEL 4
> #define AVX512VL_X86_ISA_LEVEL 4
> #define AVX512BW_X86_ISA_LEVEL 4
> +#define AVX512DQ_X86_ISA_LEVEL 4
>
> /* ISA level >= 3 guaranteed includes. */
> #define AVX_X86_ISA_LEVEL 3
> #define AVX2_X86_ISA_LEVEL 3
> #define BMI2_X86_ISA_LEVEL 3
> +#define MOVBE_X86_ISA_LEVEL 3
>
> /* NB: This feature is enabled when ISA level >= 3, which was disabled
> for the following CPUs:
> @@ -89,6 +91,14 @@
> when ISA level < 3. */
> #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
>
> +/* ISA level >= 2 guaranteed includes. */
> +#define SSE4_2_X86_ISA_LEVEL 2
> +#define SSSE3_X86_ISA_LEVEL 2
> +
> +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be
> + affected by this. */
/* Features enabled when ISA level >= 2. */
> +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> +
> /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> runtime checks. They differ in two ways.
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2] x86: Add more feature definitions to isa-level.h
2022-06-28 2:29 ` H.J. Lu
@ 2022-06-28 2:34 ` Noah Goldstein
2022-06-28 2:38 ` H.J. Lu
0 siblings, 1 reply; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 2:34 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > This commit doesn't change anything in itself. It is just to add
> > definitions that will be needed by future patches.
> > ---
> > sysdeps/x86/isa-level.h | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > index f293aea906..024d1deb80 100644
> > --- a/sysdeps/x86/isa-level.h
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -71,11 +71,13 @@
> > #define AVX512F_X86_ISA_LEVEL 4
> > #define AVX512VL_X86_ISA_LEVEL 4
> > #define AVX512BW_X86_ISA_LEVEL 4
> > +#define AVX512DQ_X86_ISA_LEVEL 4
> >
> > /* ISA level >= 3 guaranteed includes. */
> > #define AVX_X86_ISA_LEVEL 3
> > #define AVX2_X86_ISA_LEVEL 3
> > #define BMI2_X86_ISA_LEVEL 3
> > +#define MOVBE_X86_ISA_LEVEL 3
> >
> > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > for the following CPUs:
> > @@ -89,6 +91,14 @@
> > when ISA level < 3. */
> > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> >
> > +/* ISA level >= 2 guaranteed includes. */
Have a comment for ISA level 2 here.
> > +#define SSE4_2_X86_ISA_LEVEL 2
> > +#define SSSE3_X86_ISA_LEVEL 2
> > +
> > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be
> > + affected by this. */
>
> /* Features enabled when ISA level >= 2. */
Hm? This is singular.
>
> > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > +
> > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > runtime checks. They differ in two ways.
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2] x86: Add more feature definitions to isa-level.h
2022-06-28 2:34 ` Noah Goldstein
@ 2022-06-28 2:38 ` H.J. Lu
2022-06-28 2:41 ` Noah Goldstein
0 siblings, 1 reply; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 2:38 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 7:34 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > This commit doesn't change anything in itself. It is just to add
> > > definitions that will be needed by future patches.
> > > ---
> > > sysdeps/x86/isa-level.h | 10 ++++++++++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > index f293aea906..024d1deb80 100644
> > > --- a/sysdeps/x86/isa-level.h
> > > +++ b/sysdeps/x86/isa-level.h
> > > @@ -71,11 +71,13 @@
> > > #define AVX512F_X86_ISA_LEVEL 4
> > > #define AVX512VL_X86_ISA_LEVEL 4
> > > #define AVX512BW_X86_ISA_LEVEL 4
> > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > >
> > > /* ISA level >= 3 guaranteed includes. */
> > > #define AVX_X86_ISA_LEVEL 3
> > > #define AVX2_X86_ISA_LEVEL 3
> > > #define BMI2_X86_ISA_LEVEL 3
> > > +#define MOVBE_X86_ISA_LEVEL 3
> > >
> > > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > for the following CPUs:
> > > @@ -89,6 +91,14 @@
> > > when ISA level < 3. */
> > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > >
> > > +/* ISA level >= 2 guaranteed includes. */
>
> Have a comment for ISA level 2 here.
ISA is included. But arch features can be enabled/disabled.
> > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > +#define SSSE3_X86_ISA_LEVEL 2
> > > +
> > > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be
> > > + affected by this. */
> >
> > /* Features enabled when ISA level >= 2. */
>
> Hm? This is singular.
Will more be added?
>
> >
> > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > +
> > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > runtime checks. They differ in two ways.
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > H.J.
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2] x86: Add more feature definitions to isa-level.h
2022-06-28 2:38 ` H.J. Lu
@ 2022-06-28 2:41 ` Noah Goldstein
2022-06-28 3:03 ` H.J. Lu
0 siblings, 1 reply; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 2:41 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 7:39 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 7:34 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > >
> > > > This commit doesn't change anything in itself. It is just to add
> > > > definitions that will be needed by future patches.
> > > > ---
> > > > sysdeps/x86/isa-level.h | 10 ++++++++++
> > > > 1 file changed, 10 insertions(+)
> > > >
> > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > index f293aea906..024d1deb80 100644
> > > > --- a/sysdeps/x86/isa-level.h
> > > > +++ b/sysdeps/x86/isa-level.h
> > > > @@ -71,11 +71,13 @@
> > > > #define AVX512F_X86_ISA_LEVEL 4
> > > > #define AVX512VL_X86_ISA_LEVEL 4
> > > > #define AVX512BW_X86_ISA_LEVEL 4
> > > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > > >
> > > > /* ISA level >= 3 guaranteed includes. */
> > > > #define AVX_X86_ISA_LEVEL 3
> > > > #define AVX2_X86_ISA_LEVEL 3
> > > > #define BMI2_X86_ISA_LEVEL 3
> > > > +#define MOVBE_X86_ISA_LEVEL 3
> > > >
> > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > > for the following CPUs:
> > > > @@ -89,6 +91,14 @@
> > > > when ISA level < 3. */
> > > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > >
> > > > +/* ISA level >= 2 guaranteed includes. */
> >
> > Have a comment for ISA level 2 here.
>
> ISA is included. But arch features can be enabled/disabled.
>
> > > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > > +#define SSSE3_X86_ISA_LEVEL 2
> > > > +
> > > > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be
> > > > + affected by this. */
> > >
> > > /* Features enabled when ISA level >= 2. */
> >
> > Hm? This is singular.
>
> Will more be added?
None for this patchset. If in the future there are (with the same
affected CPU set)
I will make the comment plural.
>
> >
> > >
> > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > > +
> > > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > > runtime checks. They differ in two ways.
> > > > --
> > > > 2.34.1
> > > >
> > >
> > >
> > > --
> > > H.J.
>
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2] x86: Add more feature definitions to isa-level.h
2022-06-28 2:41 ` Noah Goldstein
@ 2022-06-28 3:03 ` H.J. Lu
0 siblings, 0 replies; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 3:03 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 7:42 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 7:39 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 7:34 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > > >
> > > > On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > > >
> > > > > This commit doesn't change anything in itself. It is just to add
> > > > > definitions that will be needed by future patches.
> > > > > ---
> > > > > sysdeps/x86/isa-level.h | 10 ++++++++++
> > > > > 1 file changed, 10 insertions(+)
> > > > >
> > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > > index f293aea906..024d1deb80 100644
> > > > > --- a/sysdeps/x86/isa-level.h
> > > > > +++ b/sysdeps/x86/isa-level.h
> > > > > @@ -71,11 +71,13 @@
> > > > > #define AVX512F_X86_ISA_LEVEL 4
> > > > > #define AVX512VL_X86_ISA_LEVEL 4
> > > > > #define AVX512BW_X86_ISA_LEVEL 4
> > > > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > > > >
> > > > > /* ISA level >= 3 guaranteed includes. */
> > > > > #define AVX_X86_ISA_LEVEL 3
> > > > > #define AVX2_X86_ISA_LEVEL 3
> > > > > #define BMI2_X86_ISA_LEVEL 3
> > > > > +#define MOVBE_X86_ISA_LEVEL 3
> > > > >
> > > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > > > for the following CPUs:
> > > > > @@ -89,6 +91,14 @@
> > > > > when ISA level < 3. */
> > > > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > > >
> > > > > +/* ISA level >= 2 guaranteed includes. */
> > >
> > > Have a comment for ISA level 2 here.
> >
> > ISA is included. But arch features can be enabled/disabled.
> >
> > > > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > > > +#define SSSE3_X86_ISA_LEVEL 2
> > > > > +
> > > > > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be
> > > > > + affected by this. */
> > > >
> > > > /* Features enabled when ISA level >= 2. */
> > >
> > > Hm? This is singular.
> >
> > Will more be added?
>
> None for this patchset. If in the future there are (with the same
> affected CPU set)
> I will make the comment plural.
Use singular then.
> >
> > >
> > > >
> > > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > > > +
> > > > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > > > runtime checks. They differ in two ways.
> > > > > --
> > > > > 2.34.1
> > > > >
> > > >
> > > >
> > > > --
> > > > H.J.
> >
> >
> >
> > --
> > H.J.
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3] x86: Add more feature definitions to isa-level.h
2022-06-28 1:04 [PATCH v1] x86: Add more feature definitions to isa-level.h Noah Goldstein
2022-06-28 1:56 ` H.J. Lu
2022-06-28 2:03 ` [PATCH v2] " Noah Goldstein
@ 2022-06-28 3:26 ` Noah Goldstein
2022-06-28 3:30 ` H.J. Lu
2022-06-28 3:49 ` [PATCH v4] " Noah Goldstein
2022-06-28 4:07 ` [PATCH v5] " Noah Goldstein
4 siblings, 1 reply; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 3:26 UTC (permalink / raw)
To: libc-alpha
This commit doesn't change anything in itself. It is just to add
definitions that will be needed by future patches.
---
sysdeps/x86/isa-level.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
index f293aea906..443631662f 100644
--- a/sysdeps/x86/isa-level.h
+++ b/sysdeps/x86/isa-level.h
@@ -71,11 +71,13 @@
#define AVX512F_X86_ISA_LEVEL 4
#define AVX512VL_X86_ISA_LEVEL 4
#define AVX512BW_X86_ISA_LEVEL 4
+#define AVX512DQ_X86_ISA_LEVEL 4
/* ISA level >= 3 guaranteed includes. */
#define AVX_X86_ISA_LEVEL 3
#define AVX2_X86_ISA_LEVEL 3
#define BMI2_X86_ISA_LEVEL 3
+#define MOVBE_X86_ISA_LEVEL 3
/* NB: This feature is enabled when ISA level >= 3, which was disabled
for the following CPUs:
@@ -89,6 +91,13 @@
when ISA level < 3. */
#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+/* ISA level >= 2 guaranteed includes. */
+#define SSE4_2_X86_ISA_LEVEL 2
+#define SSSE3_X86_ISA_LEVEL 2
+
+/* This feature is enabled when ISA level >= 2. */
+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
+
/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
runtime checks. They differ in two ways.
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3] x86: Add more feature definitions to isa-level.h
2022-06-28 3:26 ` [PATCH v3] " Noah Goldstein
@ 2022-06-28 3:30 ` H.J. Lu
2022-06-28 3:32 ` H.J. Lu
0 siblings, 1 reply; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 3:30 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> This commit doesn't change anything in itself. It is just to add
> definitions that will be needed by future patches.
> ---
> sysdeps/x86/isa-level.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> index f293aea906..443631662f 100644
> --- a/sysdeps/x86/isa-level.h
> +++ b/sysdeps/x86/isa-level.h
> @@ -71,11 +71,13 @@
> #define AVX512F_X86_ISA_LEVEL 4
> #define AVX512VL_X86_ISA_LEVEL 4
> #define AVX512BW_X86_ISA_LEVEL 4
> +#define AVX512DQ_X86_ISA_LEVEL 4
>
> /* ISA level >= 3 guaranteed includes. */
> #define AVX_X86_ISA_LEVEL 3
> #define AVX2_X86_ISA_LEVEL 3
> #define BMI2_X86_ISA_LEVEL 3
> +#define MOVBE_X86_ISA_LEVEL 3
>
> /* NB: This feature is enabled when ISA level >= 3, which was disabled
> for the following CPUs:
> @@ -89,6 +91,13 @@
> when ISA level < 3. */
> #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
>
> +/* ISA level >= 2 guaranteed includes. */
> +#define SSE4_2_X86_ISA_LEVEL 2
> +#define SSSE3_X86_ISA_LEVEL 2
Please move them immediately after MOVBE_X86_ISA_LEVEL.
> +/* This feature is enabled when ISA level >= 2. */
> +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> +
> /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> runtime checks. They differ in two ways.
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3] x86: Add more feature definitions to isa-level.h
2022-06-28 3:30 ` H.J. Lu
@ 2022-06-28 3:32 ` H.J. Lu
2022-06-28 3:35 ` Noah Goldstein
0 siblings, 1 reply; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 3:32 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > This commit doesn't change anything in itself. It is just to add
> > definitions that will be needed by future patches.
> > ---
> > sysdeps/x86/isa-level.h | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > index f293aea906..443631662f 100644
> > --- a/sysdeps/x86/isa-level.h
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -71,11 +71,13 @@
> > #define AVX512F_X86_ISA_LEVEL 4
> > #define AVX512VL_X86_ISA_LEVEL 4
> > #define AVX512BW_X86_ISA_LEVEL 4
> > +#define AVX512DQ_X86_ISA_LEVEL 4
> >
> > /* ISA level >= 3 guaranteed includes. */
> > #define AVX_X86_ISA_LEVEL 3
> > #define AVX2_X86_ISA_LEVEL 3
> > #define BMI2_X86_ISA_LEVEL 3
> > +#define MOVBE_X86_ISA_LEVEL 3
> >
> > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > for the following CPUs:
> > @@ -89,6 +91,13 @@
> > when ISA level < 3. */
> > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> >
> > +/* ISA level >= 2 guaranteed includes. */
> > +#define SSE4_2_X86_ISA_LEVEL 2
> > +#define SSSE3_X86_ISA_LEVEL 2
>
> Please move them immediately after MOVBE_X86_ISA_LEVEL.
BTW, comments should be ended with 2 spaces after '.'.
> > +/* This feature is enabled when ISA level >= 2. */
> > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > +
> > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > runtime checks. They differ in two ways.
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3] x86: Add more feature definitions to isa-level.h
2022-06-28 3:32 ` H.J. Lu
@ 2022-06-28 3:35 ` Noah Goldstein
2022-06-28 3:44 ` H.J. Lu
0 siblings, 1 reply; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 3:35 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 8:32 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > This commit doesn't change anything in itself. It is just to add
> > > definitions that will be needed by future patches.
> > > ---
> > > sysdeps/x86/isa-level.h | 9 +++++++++
> > > 1 file changed, 9 insertions(+)
> > >
> > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > index f293aea906..443631662f 100644
> > > --- a/sysdeps/x86/isa-level.h
> > > +++ b/sysdeps/x86/isa-level.h
> > > @@ -71,11 +71,13 @@
> > > #define AVX512F_X86_ISA_LEVEL 4
> > > #define AVX512VL_X86_ISA_LEVEL 4
> > > #define AVX512BW_X86_ISA_LEVEL 4
> > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > >
> > > /* ISA level >= 3 guaranteed includes. */
> > > #define AVX_X86_ISA_LEVEL 3
> > > #define AVX2_X86_ISA_LEVEL 3
> > > #define BMI2_X86_ISA_LEVEL 3
> > > +#define MOVBE_X86_ISA_LEVEL 3
> > >
> > > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > for the following CPUs:
> > > @@ -89,6 +91,13 @@
> > > when ISA level < 3. */
> > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > >
> > > +/* ISA level >= 2 guaranteed includes. */
> > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > +#define SSSE3_X86_ISA_LEVEL 2
> >
> > Please move them immediately after MOVBE_X86_ISA_LEVEL.
Personally I think it's clearer grouped by ISA level.
Can it remain this way?
ISA Level(N) Defaults
...
ISA Level(N) Features Enable
...
ISA Level(N - 1) Defualt
...
Think the question is more often "what's on at this ISA level"
as opposed to "what are the special features".
>
> BTW, comments should be ended with 2 spaces after '.'.
Which comment is missing?
>
> > > +/* This feature is enabled when ISA level >= 2. */
> > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > +
> > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > runtime checks. They differ in two ways.
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > H.J.
>
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3] x86: Add more feature definitions to isa-level.h
2022-06-28 3:35 ` Noah Goldstein
@ 2022-06-28 3:44 ` H.J. Lu
2022-06-28 3:50 ` Noah Goldstein
0 siblings, 1 reply; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 3:44 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 8:36 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:32 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > >
> > > > This commit doesn't change anything in itself. It is just to add
> > > > definitions that will be needed by future patches.
> > > > ---
> > > > sysdeps/x86/isa-level.h | 9 +++++++++
> > > > 1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > index f293aea906..443631662f 100644
> > > > --- a/sysdeps/x86/isa-level.h
> > > > +++ b/sysdeps/x86/isa-level.h
> > > > @@ -71,11 +71,13 @@
> > > > #define AVX512F_X86_ISA_LEVEL 4
> > > > #define AVX512VL_X86_ISA_LEVEL 4
> > > > #define AVX512BW_X86_ISA_LEVEL 4
> > > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > > >
> > > > /* ISA level >= 3 guaranteed includes. */
> > > > #define AVX_X86_ISA_LEVEL 3
> > > > #define AVX2_X86_ISA_LEVEL 3
> > > > #define BMI2_X86_ISA_LEVEL 3
> > > > +#define MOVBE_X86_ISA_LEVEL 3
> > > >
> > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > > for the following CPUs:
> > > > @@ -89,6 +91,13 @@
> > > > when ISA level < 3. */
> > > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > >
> > > > +/* ISA level >= 2 guaranteed includes. */
> > > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > > +#define SSSE3_X86_ISA_LEVEL 2
> > >
> > > Please move them immediately after MOVBE_X86_ISA_LEVEL.
>
>
> Personally I think it's clearer grouped by ISA level.
ISAs are used with X86_ISA_CPU_FEATURE_USABLE_P and
features are used with X86_ISA_CPU_FEATURES_ARCH_P.
I think grouping them together is better.
> Can it remain this way?
>
> ISA Level(N) Defaults
> ...
>
> ISA Level(N) Features Enable
> ...
>
> ISA Level(N - 1) Defualt
> ...
>
>
> Think the question is more often "what's on at this ISA level"
> as opposed to "what are the special features".
>
> >
> > BTW, comments should be ended with 2 spaces after '.'.
>
> Which comment is missing?
I may be wrong.
>
> >
> > > > +/* This feature is enabled when ISA level >= 2. */
> > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > > +
> > > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > > runtime checks. They differ in two ways.
> > > > --
> > > > 2.34.1
> > > >
> > >
> > >
> > > --
> > > H.J.
> >
> >
> >
> > --
> > H.J.
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4] x86: Add more feature definitions to isa-level.h
2022-06-28 1:04 [PATCH v1] x86: Add more feature definitions to isa-level.h Noah Goldstein
` (2 preceding siblings ...)
2022-06-28 3:26 ` [PATCH v3] " Noah Goldstein
@ 2022-06-28 3:49 ` Noah Goldstein
2022-06-28 3:58 ` H.J. Lu
2022-06-28 4:07 ` [PATCH v5] " Noah Goldstein
4 siblings, 1 reply; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 3:49 UTC (permalink / raw)
To: libc-alpha
This commit doesn't change anything in itself. It is just to add
definitions that will be needed by future patches.
---
sysdeps/x86/isa-level.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
index f293aea906..2cbce25840 100644
--- a/sysdeps/x86/isa-level.h
+++ b/sysdeps/x86/isa-level.h
@@ -67,15 +67,29 @@
/* Depending on the minimum ISA level, a feature check result can be a
compile-time constant.. */
+
+/* ISA CPU_FEATURE_USABLE_P defaults. */
+
/* ISA level >= 4 guaranteed includes. */
#define AVX512F_X86_ISA_LEVEL 4
#define AVX512VL_X86_ISA_LEVEL 4
#define AVX512BW_X86_ISA_LEVEL 4
+#define AVX512DQ_X86_ISA_LEVEL 4
/* ISA level >= 3 guaranteed includes. */
#define AVX_X86_ISA_LEVEL 3
#define AVX2_X86_ISA_LEVEL 3
#define BMI2_X86_ISA_LEVEL 3
+#define MOVBE_X86_ISA_LEVEL 3
+
+/* ISA level >= 2 guaranteed includes. */
+#define SSE4_2_X86_ISA_LEVEL 2
+#define SSSE3_X86_ISA_LEVEL 2
+
+
+/* ISA CPU_FEATURES_ARCH_P defaults. */
+
+/* Isa level >= 3 feature(s) enabled. */
/* NB: This feature is enabled when ISA level >= 3, which was disabled
for the following CPUs:
@@ -89,6 +103,9 @@
when ISA level < 3. */
#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+/* Isa level >= 2 feature(s) enabled. */
+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
+
/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
runtime checks. They differ in two ways.
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3] x86: Add more feature definitions to isa-level.h
2022-06-28 3:44 ` H.J. Lu
@ 2022-06-28 3:50 ` Noah Goldstein
0 siblings, 0 replies; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 3:50 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 8:45 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:36 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 8:32 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > > >
> > > > On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > > >
> > > > > This commit doesn't change anything in itself. It is just to add
> > > > > definitions that will be needed by future patches.
> > > > > ---
> > > > > sysdeps/x86/isa-level.h | 9 +++++++++
> > > > > 1 file changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > > index f293aea906..443631662f 100644
> > > > > --- a/sysdeps/x86/isa-level.h
> > > > > +++ b/sysdeps/x86/isa-level.h
> > > > > @@ -71,11 +71,13 @@
> > > > > #define AVX512F_X86_ISA_LEVEL 4
> > > > > #define AVX512VL_X86_ISA_LEVEL 4
> > > > > #define AVX512BW_X86_ISA_LEVEL 4
> > > > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > > > >
> > > > > /* ISA level >= 3 guaranteed includes. */
> > > > > #define AVX_X86_ISA_LEVEL 3
> > > > > #define AVX2_X86_ISA_LEVEL 3
> > > > > #define BMI2_X86_ISA_LEVEL 3
> > > > > +#define MOVBE_X86_ISA_LEVEL 3
> > > > >
> > > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > > > for the following CPUs:
> > > > > @@ -89,6 +91,13 @@
> > > > > when ISA level < 3. */
> > > > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > > >
> > > > > +/* ISA level >= 2 guaranteed includes. */
> > > > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > > > +#define SSSE3_X86_ISA_LEVEL 2
> > > >
> > > > Please move them immediately after MOVBE_X86_ISA_LEVEL.
> >
> >
> > Personally I think it's clearer grouped by ISA level.
>
> ISAs are used with X86_ISA_CPU_FEATURE_USABLE_P and
> features are used with X86_ISA_CPU_FEATURES_ARCH_P.
> I think grouping them together is better.
Okay. Done in V4.
>
> > Can it remain this way?
> >
> > ISA Level(N) Defaults
> > ...
> >
> > ISA Level(N) Features Enable
> > ...
> >
> > ISA Level(N - 1) Defualt
> > ...
> >
> >
> > Think the question is more often "what's on at this ISA level"
> > as opposed to "what are the special features".
> >
> > >
> > > BTW, comments should be ended with 2 spaces after '.'.
> >
> > Which comment is missing?
>
> I may be wrong.
>
> >
> > >
> > > > > +/* This feature is enabled when ISA level >= 2. */
> > > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > > > +
> > > > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > > > runtime checks. They differ in two ways.
> > > > > --
> > > > > 2.34.1
> > > > >
> > > >
> > > >
> > > > --
> > > > H.J.
> > >
> > >
> > >
> > > --
> > > H.J.
>
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4] x86: Add more feature definitions to isa-level.h
2022-06-28 3:49 ` [PATCH v4] " Noah Goldstein
@ 2022-06-28 3:58 ` H.J. Lu
2022-06-28 4:07 ` Noah Goldstein
0 siblings, 1 reply; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 3:58 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 8:49 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> This commit doesn't change anything in itself. It is just to add
> definitions that will be needed by future patches.
> ---
> sysdeps/x86/isa-level.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> index f293aea906..2cbce25840 100644
> --- a/sysdeps/x86/isa-level.h
> +++ b/sysdeps/x86/isa-level.h
> @@ -67,15 +67,29 @@
> /* Depending on the minimum ISA level, a feature check result can be a
> compile-time constant.. */
>
> +
> +/* ISA CPU_FEATURE_USABLE_P defaults. */
What does "defaults" mean? "For X86_ISA_CPU_FEATURE_USABLE_P"?
> +
> /* ISA level >= 4 guaranteed includes. */
> #define AVX512F_X86_ISA_LEVEL 4
> #define AVX512VL_X86_ISA_LEVEL 4
> #define AVX512BW_X86_ISA_LEVEL 4
> +#define AVX512DQ_X86_ISA_LEVEL 4
>
> /* ISA level >= 3 guaranteed includes. */
> #define AVX_X86_ISA_LEVEL 3
> #define AVX2_X86_ISA_LEVEL 3
> #define BMI2_X86_ISA_LEVEL 3
> +#define MOVBE_X86_ISA_LEVEL 3
> +
> +/* ISA level >= 2 guaranteed includes. */
> +#define SSE4_2_X86_ISA_LEVEL 2
> +#define SSSE3_X86_ISA_LEVEL 2
> +
> +
> +/* ISA CPU_FEATURES_ARCH_P defaults. */
"For X86_ISA_CPU_FEATURES_ARCH_P"?
> +
> +/* Isa level >= 3 feature(s) enabled. */
No need for this. Some features may be disabled.
>
> /* NB: This feature is enabled when ISA level >= 3, which was disabled
> for the following CPUs:
> @@ -89,6 +103,9 @@
> when ISA level < 3. */
> #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
>
> +/* Isa level >= 2 feature(s) enabled. */
These are not features in ISAs. "Feature(s) enabled when ISA level >= 2"?
> +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> +
> /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> runtime checks. They differ in two ways.
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5] x86: Add more feature definitions to isa-level.h
2022-06-28 1:04 [PATCH v1] x86: Add more feature definitions to isa-level.h Noah Goldstein
` (3 preceding siblings ...)
2022-06-28 3:49 ` [PATCH v4] " Noah Goldstein
@ 2022-06-28 4:07 ` Noah Goldstein
2022-06-28 14:38 ` H.J. Lu
4 siblings, 1 reply; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 4:07 UTC (permalink / raw)
To: libc-alpha
This commit doesn't change anything in itself. It is just to add
definitions that will be needed by future patches.
---
sysdeps/x86/isa-level.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
index f293aea906..77f9e2c0c3 100644
--- a/sysdeps/x86/isa-level.h
+++ b/sysdeps/x86/isa-level.h
@@ -67,15 +67,27 @@
/* Depending on the minimum ISA level, a feature check result can be a
compile-time constant.. */
+
+/* For CPU_FEATURE_USABLE_P. */
+
/* ISA level >= 4 guaranteed includes. */
#define AVX512F_X86_ISA_LEVEL 4
#define AVX512VL_X86_ISA_LEVEL 4
#define AVX512BW_X86_ISA_LEVEL 4
+#define AVX512DQ_X86_ISA_LEVEL 4
/* ISA level >= 3 guaranteed includes. */
#define AVX_X86_ISA_LEVEL 3
#define AVX2_X86_ISA_LEVEL 3
#define BMI2_X86_ISA_LEVEL 3
+#define MOVBE_X86_ISA_LEVEL 3
+
+/* ISA level >= 2 guaranteed includes. */
+#define SSE4_2_X86_ISA_LEVEL 2
+#define SSSE3_X86_ISA_LEVEL 2
+
+
+/* For X86_ISA_CPU_FEATURES_ARCH_P. */
/* NB: This feature is enabled when ISA level >= 3, which was disabled
for the following CPUs:
@@ -89,6 +101,9 @@
when ISA level < 3. */
#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
+/* Feature(s) enabled when ISA level >= 2. */
+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
+
/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
runtime checks. They differ in two ways.
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4] x86: Add more feature definitions to isa-level.h
2022-06-28 3:58 ` H.J. Lu
@ 2022-06-28 4:07 ` Noah Goldstein
0 siblings, 0 replies; 20+ messages in thread
From: Noah Goldstein @ 2022-06-28 4:07 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 8:59 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:49 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > This commit doesn't change anything in itself. It is just to add
> > definitions that will be needed by future patches.
> > ---
> > sysdeps/x86/isa-level.h | 17 +++++++++++++++++
> > 1 file changed, 17 insertions(+)
> >
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > index f293aea906..2cbce25840 100644
> > --- a/sysdeps/x86/isa-level.h
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -67,15 +67,29 @@
> > /* Depending on the minimum ISA level, a feature check result can be a
> > compile-time constant.. */
> >
> > +
> > +/* ISA CPU_FEATURE_USABLE_P defaults. */
>
> What does "defaults" mean? "For X86_ISA_CPU_FEATURE_USABLE_P"?
Done in V5
>
> > +
> > /* ISA level >= 4 guaranteed includes. */
> > #define AVX512F_X86_ISA_LEVEL 4
> > #define AVX512VL_X86_ISA_LEVEL 4
> > #define AVX512BW_X86_ISA_LEVEL 4
> > +#define AVX512DQ_X86_ISA_LEVEL 4
> >
> > /* ISA level >= 3 guaranteed includes. */
> > #define AVX_X86_ISA_LEVEL 3
> > #define AVX2_X86_ISA_LEVEL 3
> > #define BMI2_X86_ISA_LEVEL 3
> > +#define MOVBE_X86_ISA_LEVEL 3
> > +
> > +/* ISA level >= 2 guaranteed includes. */
> > +#define SSE4_2_X86_ISA_LEVEL 2
> > +#define SSSE3_X86_ISA_LEVEL 2
> > +
> > +
> > +/* ISA CPU_FEATURES_ARCH_P defaults. */
>
> "For X86_ISA_CPU_FEATURES_ARCH_P"?
Done in V5
>
> > +
> > +/* Isa level >= 3 feature(s) enabled. */
>
> No need for this. Some features may be disabled.
Done in V5
>
> >
> > /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > for the following CPUs:
> > @@ -89,6 +103,9 @@
> > when ISA level < 3. */
> > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> >
> > +/* Isa level >= 2 feature(s) enabled. */
>
> These are not features in ISAs. "Feature(s) enabled when ISA level >= 2"?
Done in V5
>
> > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > +
> > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > runtime checks. They differ in two ways.
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5] x86: Add more feature definitions to isa-level.h
2022-06-28 4:07 ` [PATCH v5] " Noah Goldstein
@ 2022-06-28 14:38 ` H.J. Lu
0 siblings, 0 replies; 20+ messages in thread
From: H.J. Lu @ 2022-06-28 14:38 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Mon, Jun 27, 2022 at 9:07 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> This commit doesn't change anything in itself. It is just to add
> definitions that will be needed by future patches.
> ---
> sysdeps/x86/isa-level.h | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> index f293aea906..77f9e2c0c3 100644
> --- a/sysdeps/x86/isa-level.h
> +++ b/sysdeps/x86/isa-level.h
> @@ -67,15 +67,27 @@
> /* Depending on the minimum ISA level, a feature check result can be a
> compile-time constant.. */
>
> +
> +/* For CPU_FEATURE_USABLE_P. */
> +
> /* ISA level >= 4 guaranteed includes. */
> #define AVX512F_X86_ISA_LEVEL 4
> #define AVX512VL_X86_ISA_LEVEL 4
> #define AVX512BW_X86_ISA_LEVEL 4
> +#define AVX512DQ_X86_ISA_LEVEL 4
>
> /* ISA level >= 3 guaranteed includes. */
> #define AVX_X86_ISA_LEVEL 3
> #define AVX2_X86_ISA_LEVEL 3
> #define BMI2_X86_ISA_LEVEL 3
> +#define MOVBE_X86_ISA_LEVEL 3
> +
> +/* ISA level >= 2 guaranteed includes. */
> +#define SSE4_2_X86_ISA_LEVEL 2
> +#define SSSE3_X86_ISA_LEVEL 2
> +
> +
> +/* For X86_ISA_CPU_FEATURES_ARCH_P. */
>
> /* NB: This feature is enabled when ISA level >= 3, which was disabled
> for the following CPUs:
> @@ -89,6 +101,9 @@
> when ISA level < 3. */
> #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
>
> +/* Feature(s) enabled when ISA level >= 2. */
> +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> +
> /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> runtime checks. They differ in two ways.
> --
> 2.34.1
>
LGTM.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-06-28 14:39 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
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2022-06-28 1:04 [PATCH v1] x86: Add more feature definitions to isa-level.h Noah Goldstein
2022-06-28 1:56 ` H.J. Lu
2022-06-28 2:04 ` Noah Goldstein
2022-06-28 2:03 ` [PATCH v2] " Noah Goldstein
2022-06-28 2:29 ` H.J. Lu
2022-06-28 2:34 ` Noah Goldstein
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2022-06-28 2:41 ` Noah Goldstein
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2022-06-28 3:26 ` [PATCH v3] " Noah Goldstein
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2022-06-28 3:32 ` H.J. Lu
2022-06-28 3:35 ` Noah Goldstein
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2022-06-28 3:50 ` Noah Goldstein
2022-06-28 3:49 ` [PATCH v4] " Noah Goldstein
2022-06-28 3:58 ` H.J. Lu
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2022-06-28 4:07 ` [PATCH v5] " Noah Goldstein
2022-06-28 14:38 ` H.J. Lu
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