From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112f.google.com (mail-yw1-x112f.google.com [IPv6:2607:f8b0:4864:20::112f]) by sourceware.org (Postfix) with ESMTPS id 8C319383576E for ; Tue, 28 Jun 2022 02:04:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8C319383576E Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-3177f4ce3e2so102687227b3.5 for ; Mon, 27 Jun 2022 19:04:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NIRGhglJwhXkd1Zg3DEBxECESye1ZRV9Ih02krm9M/U=; b=GPhfK2EokKxv+sE7vT/fcbZ/6STCglU9s9AeYVoY93qcHkvt308CQgMxP6II6sK9XH Q4xiv+BW1a8BQefCILO2Y2zI9GipmDwhW81XU0t3iwgP+0dEPRF9y6+lLGQ9JYeOsGtB eO81OrLP3CPPshr33c74Wtw1iHO567J5YI0cA6z6Uktrvkp//fT/INadSw/nATQ2bJLb fMqmfeOMcSl3Rnmher6gR0f+fOMFJ25qdQeI8hl/BLZY/h0GZEuHy5SPG96e0pPtIihW 45VYVX9M3QBumDwQQuUfQmDCp9CuAjOLKzmg14DN5NiddfjIAfDkjMf3emMDWUf1xPT8 QBVg== X-Gm-Message-State: AJIora+C3Vh7iez6xqK74iN0TBNZEZraqLFImzIGJZxGs1/hFTo3ehiY hxKdQN/oFqBj9TZdc4cG+yHhKakyeUnii7HB7igyhNbgRx8= X-Google-Smtp-Source: AGRyM1vNS6CBzeBODczvxum8TYipue4Ro/7aWzwbqG8whCp8lK4A3iRgSRYZftYsfp6jRBA//rQqw/WRubVZCxr9xdA= X-Received: by 2002:a81:1406:0:b0:317:9cca:6fe6 with SMTP id 6-20020a811406000000b003179cca6fe6mr18507684ywu.287.1656381874991; Mon, 27 Jun 2022 19:04:34 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> In-Reply-To: From: Noah Goldstein Date: Mon, 27 Jun 2022 19:04:24 -0700 Message-ID: Subject: Re: [PATCH v1] x86: Add more feature definitions to isa-level.h To: "H.J. Lu" Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 02:04:45 -0000 On Mon, Jun 27, 2022 at 6:57 PM H.J. Lu wrote: > > On Mon, Jun 27, 2022 at 6:05 PM Noah Goldstein wrote: > > > > This commit doesn't change anything in itself. It is just to add > > definitions that will be needed by future patches. > > --- > > sysdeps/x86/isa-level.h | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > > index f293aea906..f5ca625c21 100644 > > --- a/sysdeps/x86/isa-level.h > > +++ b/sysdeps/x86/isa-level.h > > @@ -71,11 +71,13 @@ > > #define AVX512F_X86_ISA_LEVEL 4 > > #define AVX512VL_X86_ISA_LEVEL 4 > > #define AVX512BW_X86_ISA_LEVEL 4 > > +#define AVX512DQ_X86_ISA_LEVEL 4 > > > > /* ISA level >= 3 guaranteed includes. */ > > #define AVX_X86_ISA_LEVEL 3 > > #define AVX2_X86_ISA_LEVEL 3 > > #define BMI2_X86_ISA_LEVEL 3 > > +#define MOVBE_X86_ISA_LEVEL 3 > > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > > for the following CPUs: > > @@ -89,6 +91,11 @@ > > when ISA level < 3. */ > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > > > +/* ISA level >= 2 guaranteed includes. */ > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 > > This should be defined as enabled/disabled, similarly to > AVX_Fast_Unaligned_Load_X86_ISA_LEVEL. Added a comment in the same vein as AVX_Fast_... I don't think this overrides the natural choice of any CPU so essentially said as much. > > > +#define SSE4_2_X86_ISA_LEVEL 2 > > +#define SSSE3_X86_ISA_LEVEL 2 > > + > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > > runtime checks. They differ in two ways. > > -- > > 2.34.1 > > > > > -- > H.J.