From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by sourceware.org (Postfix) with ESMTPS id A47B63857C56 for ; Tue, 18 Jan 2022 21:51:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A47B63857C56 Received: by mail-pj1-x1029.google.com with SMTP id h12so569779pjq.3 for ; Tue, 18 Jan 2022 13:51:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rWP5joveNs5q8yUddgPdDfWsogDY8iksG3pgThMN208=; b=kixTw6lJKAHQqw4yEjdw+G3TXthyMhyQFtXf+mfB2JmuW/2gchwl79XpDwEpsl0FA6 NvOPFFRw+szVNTjj1uBgcHXJX5H7lQlC+fswimb8vXOZhmhkuT8sbq/kxIBjyFNfzf2/ 6COBEA1dfwdTdP8VZrbqUpB6qJ6veMbrJczJCdXmAQzs+aBzK9WzpwNvIWTyXv5EPUtV /yo985YmDb9zX+Fm8KNtYAzSHzeKL4/GXiK4M79qjOs0/vN81JIjL7Wt3ougbUfVM3VJ 5SdH8g4Y57Uu6MVbAg/gUxPSBusI7EMZeAwkFhDybkMFxCPDY0GekTvY+KueGswfh6wO iOyw== X-Gm-Message-State: AOAM531vDXn5umXF+dqmi6ba7GuHOMiPFTWh/8EZFs3zhwYwDSj6oANE KLgxgD4ix2kIyh3b/N2H426+J26lnS2tFp8iAew= X-Google-Smtp-Source: ABdhPJz/QhBswb/gWzjL7AXeqRNzmwb+tEW92iD4E8tuDUf++3gBxxID6M/f60hkLEus7+Fke32XIqbDMEF5z/QMRrU= X-Received: by 2002:a17:90a:9104:: with SMTP id k4mr635528pjo.87.1642542689754; Tue, 18 Jan 2022 13:51:29 -0800 (PST) MIME-Version: 1.0 References: <20220118212940.2051376-1-hjl.tools@gmail.com> In-Reply-To: <20220118212940.2051376-1-hjl.tools@gmail.com> From: Noah Goldstein Date: Tue, 18 Jan 2022 15:51:18 -0600 Message-ID: Subject: Re: [PATCH v2] x86: Black list more Intel CPUs for TSX [BZ #27398] To: "H.J. Lu" Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Jan 2022 21:51:32 -0000 On Tue, Jan 18, 2022 at 3:29 PM H.J. Lu wrote: > > Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in: > > https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html > > This fixes BZ #27398. > --- > sysdeps/x86/cpu-features.c | 34 +++++++++++++++++++++++++++++++--- > 1 file changed, 31 insertions(+), 3 deletions(-) > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > index 772ccf8e91..514226b378 100644 > --- a/sysdeps/x86/cpu-features.c > +++ b/sysdeps/x86/cpu-features.c > @@ -507,11 +507,39 @@ init_cpu_features (struct cpu_features *cpu_features) > break; > } > > - /* Disable TSX on some Haswell processors to avoid TSX on kernels that > - weren't updated with the latest microcode package (which disables > - broken feature by default). */ > + /* Disable TSX on some processors to avoid TSX on kernels that > + weren't updated with the latest microcode package (which > + disables broken feature by default). */ > switch (model) > { > + case 0x55: > + if (stepping <= 5) > + goto disable_tsx; > + break; > + case 0x8e: > + /* NB: Although the errata documents that for model == 0x8e, > + only 0xb stepping or lower are impacted, the intention of > + the errata was to disable TSX on all client processors on > + all steppings. Include 0xc stepping which is an Intel > + Core i7-8665U, a client mobile processor. */ > + case 0x9e: > + if (stepping > 0xc) > + break; > + /* Fall through. */ > + case 0x4e: > + case 0x5e: > + { > + /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for > + processors listed in: > + > +https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html > + */ > +disable_tsx: > + CPU_FEATURE_UNSET (cpu_features, HLE); > + CPU_FEATURE_UNSET (cpu_features, RTM); > + CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT); > + } > + break; > case 0x3f: > /* Xeon E7 v3 with stepping >= 4 has working TSX. */ > if (stepping >= 4) > -- > 2.34.1 > LGTM.