From: Noah Goldstein <goldstein.w.n@gmail.com>
To: Adhemerval Zanella Netto <adhemerval.zanella@linaro.org>
Cc: GNU C Library <libc-alpha@sourceware.org>,
Florian Weimer <fweimer@redhat.com>
Subject: Re: [PATCH v9 6/9] x86: Add AVX2 optimized chacha20
Date: Wed, 13 Jul 2022 13:24:19 -0700 [thread overview]
Message-ID: <CAFUsyfLC8nn-AjNFYCM_XWiLbnJ3fuKHsgKLjB3=T6-qrxYYRg@mail.gmail.com> (raw)
In-Reply-To: <ec32bff6-5f16-b17e-6ac5-9dad7324ef74@linaro.org>
On Wed, Jul 13, 2022 at 12:32 PM Adhemerval Zanella Netto
<adhemerval.zanella@linaro.org> wrote:
>
>
>
> On 13/07/22 15:07, Noah Goldstein wrote:
> > On Wed, Jul 13, 2022 at 10:40 AM Adhemerval Zanella via Libc-alpha
> > <libc-alpha@sourceware.org> wrote:
> >>
> >> From: Adhemerval Zanella Netto <adhemerval.zanella@linaro.org>
> >> diff --git a/sysdeps/x86_64/chacha20_arch.h b/sysdeps/x86_64/chacha20_arch.h
> >> index 5738c840a9..bfdc6c0a36 100644
> >> --- a/sysdeps/x86_64/chacha20_arch.h
> >> +++ b/sysdeps/x86_64/chacha20_arch.h
> >> @@ -23,16 +23,26 @@
> >> unsigned int __chacha20_sse2_blocks4 (uint32_t *state, uint8_t *dst,
> >> const uint8_t *src, size_t nblks)
> >> attribute_hidden;
> >> +unsigned int __chacha20_avx2_blocks8 (uint32_t *state, uint8_t *dst,
> >> + const uint8_t *src, size_t nblks)
> >> + attribute_hidden;
> >>
> >> static inline void
> >> chacha20_crypt (uint32_t *state, uint8_t *dst, const uint8_t *src,
> >> size_t bytes)
> >> {
> >> - _Static_assert (CHACHA20_BUFSIZE % 4 == 0,
> >> - "CHACHA20_BUFSIZE not multiple of 4");
> >> - _Static_assert (CHACHA20_BUFSIZE >= CHACHA20_BLOCK_SIZE * 4,
> >> - "CHACHA20_BUFSIZE <= CHACHA20_BLOCK_SIZE * 4");
> >> + _Static_assert (CHACHA20_BUFSIZE % 4 == 0 && CHACHA20_BUFSIZE % 8 == 0,
> >> + "CHACHA20_BUFSIZE not multiple of 4 or 8");
> >> + _Static_assert (CHACHA20_BUFSIZE >= CHACHA20_BLOCK_SIZE * 8,
> >> + "CHACHA20_BUFSIZE < CHACHA20_BLOCK_SIZE * 8");
> >> + const struct cpu_features* cpu_features = __get_cpu_features ();
> >>
> >> - __chacha20_sse2_blocks4 (state, dst, src,
> >> - CHACHA20_BUFSIZE / CHACHA20_BLOCK_SIZE);
> >> + /* AVX2 version uses vzeroupper, so disable it if RTM is enabled. */
> >
> > Since `arc4random ()` might need to read from /dev/urandom I don't
> > think this function could ever truly be RTM safe so we may not care.>
> > If im missing something we do want to support RTM, should there be a
> > '!CPU_FEATURE_USABLE_P (cpu_features, RTM)' check for the avx2
> > implementation?
> >
> I don't fully recall the issue regarding RTM to be sincere (just that
> we had to rework some ifunc selection to handle it).
In this case we don't need to support RTM so no need.
>
> >
> >
> >> + if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> >> + && !CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
> >
> > Can you use the X86_ISA_* macro?
> >
> > In this case the code would be:
> >
> > if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER, !))
>
> Yes it would work. I have changed to the following to support the x86_64 isa
> work you have been doing:
Thanks.
>
> --
> #if MINIMUM_X86_ISA_LEVEL > 2
> __chacha20_avx2_blocks8 (state, dst, src,
> CHACHA20_BUFSIZE / CHACHA20_BLOCK_SIZE);
> #else
> const struct cpu_features* cpu_features = __get_cpu_features ();
>
> /* AVX2 version uses vzeroupper, so disable it if RTM is enabled. */
> if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER, !))
> __chacha20_avx2_blocks8 (state, dst, src,
> CHACHA20_BUFSIZE / CHACHA20_BLOCK_SIZE);
> else
> __chacha20_sse2_blocks4 (state, dst, src,
> CHACHA20_BUFSIZE / CHACHA20_BLOCK_SIZE);
> #endif
> --
>
> I am aware that X86_ISA_CPU_FEATURE_USABLE_P will const-eval to 1 if the
> ISA is higher enough, but I think the code is slight clear (specially
> when the reader is not aware of the const-eval).
>
Think this is good. Thanks and sorry for the last minute requests.
>
> >
> >
> >> + __chacha20_avx2_blocks8 (state, dst, src,
> >> + CHACHA20_BUFSIZE / CHACHA20_BLOCK_SIZE);
> >> + else
> >> + __chacha20_sse2_blocks4 (state, dst, src,
> >> + CHACHA20_BUFSIZE / CHACHA20_BLOCK_SIZE);
> >> }
> >> --
> >> 2.34.1
> >>
next prev parent reply other threads:[~2022-07-13 20:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-13 17:36 [PATCH v9 0/9] Add arc4random support Adhemerval Zanella
2022-07-13 17:36 ` [PATCH v9 1/9] stdlib: Add arc4random, arc4random_buf, and arc4random_uniform (BZ #4417) Adhemerval Zanella
2022-07-13 17:36 ` [PATCH v9 2/9] stdlib: Add arc4random tests Adhemerval Zanella
2022-07-13 17:36 ` [PATCH v9 3/9] benchtests: Add arc4random benchtest Adhemerval Zanella
2022-07-13 17:36 ` [PATCH v9 4/9] aarch64: Add optimized chacha20 Adhemerval Zanella
2022-07-13 17:36 ` [PATCH v9 5/9] x86: Add SSE2 " Adhemerval Zanella
2022-07-13 18:12 ` Noah Goldstein
2022-07-13 18:20 ` Adhemerval Zanella Netto
2022-07-13 18:22 ` Noah Goldstein
2022-07-13 18:27 ` Noah Goldstein
2022-07-13 18:29 ` Adhemerval Zanella Netto
2022-07-13 18:53 ` Noah Goldstein
2022-07-13 17:36 ` [PATCH v9 6/9] x86: Add AVX2 " Adhemerval Zanella
2022-07-13 18:07 ` Noah Goldstein
2022-07-13 19:31 ` Adhemerval Zanella Netto
2022-07-13 20:24 ` Noah Goldstein [this message]
2022-07-13 20:16 ` Florian Weimer
2022-07-13 20:23 ` Noah Goldstein
2022-07-13 17:36 ` [PATCH v9 7/9] powerpc64: Add " Adhemerval Zanella
2022-07-13 17:36 ` [PATCH v9 8/9] s390x: " Adhemerval Zanella
2022-07-13 17:36 ` [PATCH v9 9/9] manual: Add documentation for arc4random functions Adhemerval Zanella
2022-07-14 10:03 ` Mark Harris
2022-07-14 11:08 ` Adhemerval Zanella Netto
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