From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112e.google.com (mail-yw1-x112e.google.com [IPv6:2607:f8b0:4864:20::112e]) by sourceware.org (Postfix) with ESMTPS id D4919385C324 for ; Tue, 28 Jun 2022 03:36:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D4919385C324 Received: by mail-yw1-x112e.google.com with SMTP id 00721157ae682-3176b6ed923so103663337b3.11 for ; Mon, 27 Jun 2022 20:36:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Eq+zwTbYQ5HB9Fj0CEWQjMZ26vwvCOZjFq4sZRqORW4=; b=E68oQ6RooqUs9uh7D0IJhCUZVZUINBMZjQYFHMJZXnYqAVLc2IXjL6qMCoz9//qwKJ kl2OzGkw4ZX8ncXmZuycPyLLcexDT6W3tlOH9U/A16k9tXFzH74b8qCbTf9p2oA1m7HU NF9mfuLsv3nj3htow18fNZnfbZmruPd+RfGfj1r2ihqfx7iEcVZ/7VOxBeklkZpRrk/9 3vtkedaC2D2QPd8v9DjlTLAhkvpyZrWDoDysVtsj3lJClOnKYhIOdheCmFatafVAPVW4 5O5Os2uE2U4Kbj4sDq2WI6kY3OSQhMrLdNG86Oy80edvmxSdYIcsbjhuw2TncdVP3fB9 e1RA== X-Gm-Message-State: AJIora+PQVoiOFZbbJRQU31A1ENChifB+HNc2vjPYy5GF7oBI6XiRKvh TFKlxvjTT3r18h/9X6wh1vdUjnQRa2+IqZFT+22+fpMICY+ZIA== X-Google-Smtp-Source: AGRyM1taTVjER7zuRs4sAAf4Dw+QuhTWoReSC4WjJ6qsQm90pqo9wnF2D3fcHw2RAX0fBzc8hhZfjrmdhYUvur8RKZ0= X-Received: by 2002:a81:1406:0:b0:317:9cca:6fe6 with SMTP id 6-20020a811406000000b003179cca6fe6mr18810048ywu.287.1656387366228; Mon, 27 Jun 2022 20:36:06 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> <20220628032602.218678-1-goldstein.w.n@gmail.com> In-Reply-To: From: Noah Goldstein Date: Mon, 27 Jun 2022 20:35:55 -0700 Message-ID: Subject: Re: [PATCH v3] x86: Add more feature definitions to isa-level.h To: "H.J. Lu" Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 03:36:08 -0000 On Mon, Jun 27, 2022 at 8:32 PM H.J. Lu wrote: > > On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu wrote: > > > > On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein wrote: > > > > > > This commit doesn't change anything in itself. It is just to add > > > definitions that will be needed by future patches. > > > --- > > > sysdeps/x86/isa-level.h | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > > > index f293aea906..443631662f 100644 > > > --- a/sysdeps/x86/isa-level.h > > > +++ b/sysdeps/x86/isa-level.h > > > @@ -71,11 +71,13 @@ > > > #define AVX512F_X86_ISA_LEVEL 4 > > > #define AVX512VL_X86_ISA_LEVEL 4 > > > #define AVX512BW_X86_ISA_LEVEL 4 > > > +#define AVX512DQ_X86_ISA_LEVEL 4 > > > > > > /* ISA level >= 3 guaranteed includes. */ > > > #define AVX_X86_ISA_LEVEL 3 > > > #define AVX2_X86_ISA_LEVEL 3 > > > #define BMI2_X86_ISA_LEVEL 3 > > > +#define MOVBE_X86_ISA_LEVEL 3 > > > > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > > > for the following CPUs: > > > @@ -89,6 +91,13 @@ > > > when ISA level < 3. */ > > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > > > > > +/* ISA level >= 2 guaranteed includes. */ > > > +#define SSE4_2_X86_ISA_LEVEL 2 > > > +#define SSSE3_X86_ISA_LEVEL 2 > > > > Please move them immediately after MOVBE_X86_ISA_LEVEL. Personally I think it's clearer grouped by ISA level. Can it remain this way? ISA Level(N) Defaults ... ISA Level(N) Features Enable ... ISA Level(N - 1) Defualt ... Think the question is more often "what's on at this ISA level" as opposed to "what are the special features". > > BTW, comments should be ended with 2 spaces after '.'. Which comment is missing? > > > > +/* This feature is enabled when ISA level >= 2. */ > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 > > > + > > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > > > runtime checks. They differ in two ways. > > > -- > > > 2.34.1 > > > > > > > > > -- > > H.J. > > > > -- > H.J.