From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id 9AB963858C2C for ; Sun, 2 Oct 2022 21:08:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9AB963858C2C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x534.google.com with SMTP id u21so8007160edi.9 for ; Sun, 02 Oct 2022 14:08:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=1EiqkAmvJ08IK6ZHn2kLq5FNxTQzJxAstqPD5MpR0fc=; b=l0TiH9VWSH8NAHRCZOpUUDBsn7TdqNUnnllgDJperPh7sG7jO9XBNinKcqE5Vg0qZB kEW31gk43KDdBS2j/p7FSpaiUvRzSrAHCbOOf4z/tY5bZ9yWqTeeCWPbvhN+cpXs1DCa UqBOf4eTePuzQWMiwiKzsXWl3F0/qU8fiZCj0q+B+hRgQd4xwP5CV1eT755h156pdvgz vMfHMmz4F/RKebuBn9oAPL18Wz9TPnd0jEvv534CC4axAlyL3NmpOpYltSmlcnwWVEFr 1X0jooqbTgW5Ns0/P1UBL2wQo4EwSc7rRgg1LodwH5xfQOBmnQdGAVSICsLFDeYuVusf VJjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=1EiqkAmvJ08IK6ZHn2kLq5FNxTQzJxAstqPD5MpR0fc=; b=N5ARbMBOc5Xk0bH31sgRDZSGCgElrdUlrZDHGjFIbJzONaBZeBmFPAZujd67TqKuKY y7iyQmcPV6zDSsy0XDu2xoNuVcPkTwnZzIntzG8DmDAo75QT3Xwo5uo/z79cfOAz6aiV xq62ZwaMFpn23qmg4aNUFkVzxEUyJ+lO1WsQ51IwbCsSCfWK/BuHVVtx7hDfKkWaarrB uhZvBlVME6b1uUQxdxfAFQ/TMp777diWrGPLgmOyM5fSiMjJ4p71jNwkLscTIYv+1zNM 3tUoAjmmWogKp4kfuF9Fw7bg8QWnDCGmfAJ/Rqxvn8NYuZXpRcIhppToxqL2Rjs3S7m/ e3pQ== X-Gm-Message-State: ACrzQf2QoQbryeJFt20voum3DpH9H+fvJoJFtxtNutcVzKxSUtgW9qmu bnaofCbVDoRBhfpN1kZrNfipXb1QCSqTG9A92VU= X-Google-Smtp-Source: AMsMyM4hkzphvcaiMQwr962VfAHwE4ub06Yr67dbtafY6DYcAiiJ8ovmh85QQBwkKh+2b6FI6kjjELLWc3w+JeV+6hc= X-Received: by 2002:a05:6402:3584:b0:458:d3fa:fb89 with SMTP id y4-20020a056402358400b00458d3fafb89mr4926871edc.218.1664744924421; Sun, 02 Oct 2022 14:08:44 -0700 (PDT) MIME-Version: 1.0 References: <20221002123424.3079805-1-aurelien@aurel32.net> <20221002123424.3079805-4-aurelien@aurel32.net> In-Reply-To: <20221002123424.3079805-4-aurelien@aurel32.net> From: Noah Goldstein Date: Sun, 2 Oct 2022 17:08:32 -0400 Message-ID: Subject: Re: [PATCH v2 3/6] x86-64: Require BMI2 for AVX2 (raw|w)memchr implementations To: Aurelien Jarno Cc: libc-alpha@sourceware.org, "H . J . Lu" , Sunil K Pandey Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sun, Oct 2, 2022 at 8:34 AM Aurelien Jarno wrote: > > The AVX2 memchr, rawmemchr and wmemchr implementations use the 'bzhi' > and 'sarx' instructions, which belongs to the BMI2 CPU feature. > > Fixes: acfd088a1963 ("x86: Optimize memchr-avx2.S") > Partially resolves: BZ #29611 > --- > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > index fec8790c11..7c84963d92 100644 > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > @@ -69,10 +69,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > && CPU_FEATURE_USABLE (BMI2)), > __memchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2)), > __memchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > && CPU_FEATURE_USABLE (RTM)), > __memchr_avx2_rtm) > /* ISA V2 wrapper for SSE2 implementation because the SSE2 > @@ -335,10 +337,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > && CPU_FEATURE_USABLE (BMI2)), > __rawmemchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2)), > __rawmemchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > && CPU_FEATURE_USABLE (RTM)), > __rawmemchr_avx2_rtm) > /* ISA V2 wrapper for SSE2 implementation because the SSE2 > @@ -927,10 +931,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > && CPU_FEATURE_USABLE (BMI2)), > __wmemchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, > - CPU_FEATURE_USABLE (AVX2), > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2)), > __wmemchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, > (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (BMI2) > && CPU_FEATURE_USABLE (RTM)), > __wmemchr_avx2_rtm) > /* ISA V2 wrapper for SSE2 implementation because the SSE2 > -- > 2.35.1 > LGTM.