From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x329.google.com (mail-ot1-x329.google.com [IPv6:2607:f8b0:4864:20::329]) by sourceware.org (Postfix) with ESMTPS id 74E2C385E02A for ; Wed, 10 May 2023 16:07:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 74E2C385E02A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ot1-x329.google.com with SMTP id 46e09a7af769-6aafdeab6b0so2877897a34.0 for ; Wed, 10 May 2023 09:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683734864; x=1686326864; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=dGqH2ifAtOTtd26VGTAQMZROEhmOiiGHFNFykoiAYMU=; b=lABZZcqTYgMFQCpl7I9PmOWnB7TOkH69Ac03TIuwzo1jsLFq0HwKNixvcGIOmHTtOD CbhPOdSdiUYfXepwXo5in1FNjTR2RPL0HsGcZCapWY1BvM1DbMII/TSimxC9jjtQC+ZR ZPWxKR7GiY2xIlHcVws4Qgb37JtcIcwpl/1/UFn6z1R6cC0OsOL2bpk8Wcx/uRs7mrSa 1pXsxNzrRBRNAB4EXpjXJ6oe10jkOVgs0yQk7wqBcMG+qM8SxPHrCappbiSo4dWHPG8Y VZiuRmsCHP7B7GoNDW5QD3P+2IRIWXfGR1q5AZ9pfffyPzbt1xUblMoQHE6ucO0oH3+0 y+wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683734864; x=1686326864; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dGqH2ifAtOTtd26VGTAQMZROEhmOiiGHFNFykoiAYMU=; b=XoD227zK7OxBOuG7iJqnQqKkJwubKUs5vnzGrV/sk8kefY3NLfc0pg9vN/QFSDwHHQ KAe+mPLQytdSx4Pi5GT/0hN9z19eqGA54cliAxRPY/HG194VaYz463bAze2dGTAYYuIQ NwnwLqiO2/XoQIfjcjz7n+VG8lS8Iv5lJ1zM0UKXWAgX+/sbmIbnyglagb6u7h+VYsQr d5VYSuvuO7MNzidl1YX6E1duMjzR0WezRz2fgRjnWAghOnO25+cR9gj7q9v+Xs7p5cYD XkEy86vK+CO6gBRgxtq63WpT1uKNAtSo41NU6yZwMaSr/XLr7MsmHknG5n4T3XRIfWVl w8Ag== X-Gm-Message-State: AC+VfDwX5JLdIYqP6/m96jOxxjVEWUBqCF+ime9l81dW5U9bgf+Atcz+ PV/u7QlBOX4K7XoKNZwv2KhGs6m+/0Uo1UkrjeA= X-Google-Smtp-Source: ACHHUZ6yxPwe7TJK/A0baAQ7rk1oOZE3WRV1bB4xuorsLb1xUnTkpyZ5Y5xXVNIi4pIGESUBZAuizPQPsB+BhLbxqxE= X-Received: by 2002:a9d:6d85:0:b0:6ab:1447:8817 with SMTP id x5-20020a9d6d85000000b006ab14478817mr3749396otp.17.1683734863481; Wed, 10 May 2023 09:07:43 -0700 (PDT) MIME-Version: 1.0 References: <20230424050329.1501348-1-goldstein.w.n@gmail.com> <20230510003336.637851-1-goldstein.w.n@gmail.com> In-Reply-To: From: Noah Goldstein Date: Wed, 10 May 2023 11:07:31 -0500 Message-ID: Subject: Re: [PATCH v6 1/4] x86: Increase `non_temporal_threshold` to roughly `sizeof_L3 / 4` To: "H.J. Lu" Cc: libc-alpha@sourceware.org, carlos@systemhalted.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, May 10, 2023 at 10:56=E2=80=AFAM H.J. Lu wrot= e: > > On Tue, May 9, 2023 at 5:33=E2=80=AFPM Noah Goldstein wrote: > > > > Current `non_temporal_threshold` set to roughly '3/4 * sizeof_L3 / > > ncores_per_socket'. This patch updates that value to roughly > > 'sizeof_L3 / 4` > > > > The original value (specifically dividing the `ncores_per_socket`) was > > done to limit the amount of other threads' data a `memcpy`/`memset` > > could evict. > > > > Dividing by 'ncores_per_socket', however leads to exceedingly low > > non-temporal thresholds and leads to using non-temporal stores in > > cases where REP MOVSB is multiple times faster. > > > > Furthermore, non-temporal stores are written directly to main memory > > so using it at a size much smaller than L3 can place soon to be > > accessed data much further away than it otherwise could be. As well, > > modern machines are able to detect streaming patterns (especially if > > REP MOVSB is used) and provide LRU hints to the memory subsystem. This > > in affect caps the total amount of eviction at 1/cache_associativity, > > far below meaningfully thrashing the entire cache. > > > > As best I can tell, the benchmarks that lead this small threshold > > where done comparing non-temporal stores versus standard cacheable > > stores. A better comparison (linked below) is to be REP MOVSB which, > > on the measure systems, is nearly 2x faster than non-temporal stores > > at the low-end of the previous threshold, and within 10% for over > > 100MB copies (well past even the current threshold). In cases with a > > low number of threads competing for bandwidth, REP MOVSB is ~2x faster > > up to `sizeof_L3`. > > > > The divisor of `4` is a somewhat arbitrary value. From benchmarks it > > seems Skylake and Icelake both prefer a divisor of `2`, but older CPUs > > such as Broadwell prefer something closer to `8`. This patch is meant > > to be followed up by another one to make the divisor cpu-specific, but > > in the meantime (and for easier backporting), this patch settles on > > `4` as a middle-ground. > > > > Benchmarks comparing non-temporal stores, REP MOVSB, and cacheable > > stores where done using: > > https://github.com/goldsteinn/memcpy-nt-benchmarks > > > > Sheets results (also available in pdf on the github): > > https://docs.google.com/spreadsheets/d/e/2PACX-1vS183r0rW_jRX6tG_E90m9q= VuFiMbRIJvi5VAE8yYOvEOIEEc3aSNuEsrFbuXw5c3nGboxMmrupZD7K/pubhtml > > --- > > sysdeps/x86/dl-cacheinfo.h | 70 +++++++++++++++++++++++--------------- > > 1 file changed, 43 insertions(+), 27 deletions(-) > > > > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > > index ec88945b39..4a1a5423ff 100644 > > --- a/sysdeps/x86/dl-cacheinfo.h > > +++ b/sysdeps/x86/dl-cacheinfo.h > > @@ -407,7 +407,7 @@ handle_zhaoxin (int name) > > } > > > > static void > > -get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr= , > > +get_common_cache_info (long int *shared_ptr, long int * shared_per_thr= ead_ptr, unsigned int *threads_ptr, > > long int core) > > { > > unsigned int eax; > > @@ -426,6 +426,7 @@ get_common_cache_info (long int *shared_ptr, unsign= ed int *threads_ptr, > > unsigned int family =3D cpu_features->basic.family; > > unsigned int model =3D cpu_features->basic.model; > > long int shared =3D *shared_ptr; > > + long int shared_per_thread =3D *shared_per_thread_ptr; > > unsigned int threads =3D *threads_ptr; > > bool inclusive_cache =3D true; > > bool support_count_mask =3D true; > > @@ -441,6 +442,7 @@ get_common_cache_info (long int *shared_ptr, unsign= ed int *threads_ptr, > > /* Try L2 otherwise. */ > > level =3D 2; > > shared =3D core; > > + shared_per_thread =3D core; > > threads_l2 =3D 0; > > threads_l3 =3D -1; > > } > > @@ -597,29 +599,28 @@ get_common_cache_info (long int *shared_ptr, unsi= gned int *threads_ptr, > > } > > else > > { > > -intel_bug_no_cache_info: > > - /* Assume that all logical threads share the highest cache > > - level. */ > > - threads > > - =3D ((cpu_features->features[CPUID_INDEX_1].cpuid.ebx >> 1= 6) > > - & 0xff); > > - } > > - > > - /* Cap usage of highest cache level to the number of supported > > - threads. */ > > - if (shared > 0 && threads > 0) > > - shared /=3D threads; > > + intel_bug_no_cache_info: > > + /* Assume that all logical threads share the highest cache > > + level. */ > > + threads =3D ((cpu_features->features[CPUID_INDEX_1].cpuid.ebx= >> 16) > > + & 0xff); > > + > > + /* Get per-thread size of highest level cache. */ > > + if (shared_per_thread > 0 && threads > 0) > > + shared_per_thread /=3D threads; > > + } > > } > > > > /* Account for non-inclusive L2 and L3 caches. */ > > if (!inclusive_cache) > > { > > if (threads_l2 > 0) > > - core /=3D threads_l2; > > + shared_per_thread +=3D core / threads_l2; > > shared +=3D core; > > } > > > > *shared_ptr =3D shared; > > + *shared_per_thread_ptr =3D shared_per_thread; > > *threads_ptr =3D threads; > > } > > > > @@ -629,6 +630,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_feature= s) > > /* Find out what brand of processor. */ > > long int data =3D -1; > > long int shared =3D -1; > > + long int shared_per_thread =3D -1; > > long int core =3D -1; > > unsigned int threads =3D 0; > > unsigned long int level1_icache_size =3D -1; > > @@ -649,6 +651,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_feature= s) > > data =3D handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); > > core =3D handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); > > shared =3D handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); > > + shared_per_thread =3D shared; > > > > level1_icache_size > > =3D handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); > > @@ -672,13 +675,14 @@ dl_init_cacheinfo (struct cpu_features *cpu_featu= res) > > level4_cache_size > > =3D handle_intel (_SC_LEVEL4_CACHE_SIZE, cpu_features); > > > > - get_common_cache_info (&shared, &threads, core); > > + get_common_cache_info (&shared, &shared_per_thread, &threads, co= re); > > } > > else if (cpu_features->basic.kind =3D=3D arch_kind_zhaoxin) > > { > > data =3D handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE); > > core =3D handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE); > > shared =3D handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); > > + shared_per_thread =3D shared; > > > > level1_icache_size =3D handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE); > > level1_icache_linesize =3D handle_zhaoxin (_SC_LEVEL1_ICACHE_LIN= ESIZE); > > @@ -692,13 +696,14 @@ dl_init_cacheinfo (struct cpu_features *cpu_featu= res) > > level3_cache_assoc =3D handle_zhaoxin (_SC_LEVEL3_CACHE_ASSOC); > > level3_cache_linesize =3D handle_zhaoxin (_SC_LEVEL3_CACHE_LINES= IZE); > > > > - get_common_cache_info (&shared, &threads, core); > > + get_common_cache_info (&shared, &shared_per_thread, &threads, co= re); > > } > > else if (cpu_features->basic.kind =3D=3D arch_kind_amd) > > { > > data =3D handle_amd (_SC_LEVEL1_DCACHE_SIZE); > > core =3D handle_amd (_SC_LEVEL2_CACHE_SIZE); > > shared =3D handle_amd (_SC_LEVEL3_CACHE_SIZE); > > + shared_per_thread =3D shared; > > > > level1_icache_size =3D handle_amd (_SC_LEVEL1_ICACHE_SIZE); > > level1_icache_linesize =3D handle_amd (_SC_LEVEL1_ICACHE_LINESIZ= E); > > @@ -715,6 +720,9 @@ dl_init_cacheinfo (struct cpu_features *cpu_feature= s) > > if (shared <=3D 0) > > /* No shared L3 cache. All we have is the L2 cache. */ > > shared =3D core; > > + > > + if (shared_per_thread <=3D 0) > > + shared_per_thread =3D shared; > > } > > > > cpu_features->level1_icache_size =3D level1_icache_size; > > @@ -730,17 +738,25 @@ dl_init_cacheinfo (struct cpu_features *cpu_featu= res) > > cpu_features->level3_cache_linesize =3D level3_cache_linesize; > > cpu_features->level4_cache_size =3D level4_cache_size; > > > > - /* The default setting for the non_temporal threshold is 3/4 of one > > - thread's share of the chip's cache. For most Intel and AMD proces= sors > > - with an initial release date between 2017 and 2020, a thread's ty= pical > > - share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 > > - threshold leaves 125 KBytes to 500 KBytes of the thread's data > > - in cache after a maximum temporal copy, which will maintain > > - in cache a reasonable portion of the thread's stack and other > > - active data. If the threshold is set higher than one thread's > > - share of the cache, it has a substantial risk of negatively > > - impacting the performance of other threads running on the chip. *= / > > - unsigned long int non_temporal_threshold =3D shared * 3 / 4; > > + /* The default setting for the non_temporal threshold is 1/4 of size > > + of the chip's cache. For most Intel and AMD processors with an > > + initial release date between 2017 and 2023, a thread's typical > > + share of the cache is from 18-64MB. Using the 1/4 L3 is meant to > > + estimate the point where non-temporal stores begin outcompeting > > + REP MOVSB. As well the point where the fact that non-temporal > > + stores are forced back to main memory would already occurred to t= he > > + majority of the lines in the copy. Note, concerns about the > > + entire L3 cache being evicted by the copy are mostly alleviated > > + by the fact that modern HW detects streaming patterns and > > + provides proper LRU hints so that the maximum thrashing > > + capped at 1/associativity. */ > > + unsigned long int non_temporal_threshold =3D shared / 4; > > + /* If no ERMS, we use the per-thread L3 chunking. Normal cacheable s= tores run > > + a higher risk of actually thrashing the cache as they don't have = a HW LRU > > + hint. As well, there performance in highly parallel situations is > > + noticeably worse. */ > > + if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)) > > + non_temporal_threshold =3D shared_per_thread * 3 / 4; > > /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the= value of > > 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it= is best > > if that operation cannot overflow. Minimum of 0x4040 (16448) beca= use the > > -- > > 2.34.1 > > > > LGTM. > > BTW, this is a standalone patch and can be committed separately. > Yeah, Carlos wanted to reproduce the results independently and review so waiting on that. > Thanks. > > -- > H.J.