From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by sourceware.org (Postfix) with ESMTPS id A50EF3858D1E for ; Mon, 24 Apr 2023 18:34:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A50EF3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-506b8c6bbdbso7211140a12.1 for ; Mon, 24 Apr 2023 11:34:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682361265; x=1684953265; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=YBvGaGlMxF5+bmk24XinPvZ5n/T4n5nsGdys5uk89LI=; b=KUGenVkWXrvwpUQ1HxZh+7vcbWoUE5xiHgcphq3tlehxuCnHOWrCBBv03ZAipwuoZC 17m6HYfYxpv+VYsOvFiJrIbENnWXZZ8ePA2JXIpf6V3Ai/aLF0cN1H/ZvyG86GyEo593 DAV0l6YNM9desMIVJjNXulzqVz016br4kymOQLI86M9jPZJ9iNTsFBIrPSwDtDra9S81 t+eoEjMWHkV5uMD/Bnsrnnkm5PRzNmaRofjhsUBhoBz+XFw3Vq/oaPYVZQGDHoKdNU9Y 0dmVdYUyaGKQ94oHnNFW+7YPB3NZme2zq7QaIJaoh1GbwpE7z/Ig8qu7z/Dxc7Tj4+Bz Gwqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682361265; x=1684953265; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBvGaGlMxF5+bmk24XinPvZ5n/T4n5nsGdys5uk89LI=; b=KyVgDL0H85w4mOh5QQmIUQtTWDhs0egzzkM0M6fFeZIUBq+AxJsT1rj18zZxVc49o6 jb1dL5kHFO1SgOcYPta6V9ZX75PcMAcyrjIcWsasQ6dXiw8p73S+p/62rzpq6Bj4rs9U Drs+lNvlSUdi0gMPCwPvlg/+XIGbYYTy9VNku2h+6nfgc8zrNHOxquuu/VlNO9i29gRl QwiaiOyE0lLz6SWfjOq4I1ACQRcyHO2XtUHUeD+6q4DCWTP37vhu8nOEiO/mPftLibFS lvXx9t6xrR3hNiunaE0cW+39qUPcgGhtbKAsfyiOc63NS+ac09dVyWJ19NzqLEKSMPlk cogg== X-Gm-Message-State: AAQBX9fxJ4lT+ScoONli4FmW+JpTcK5103cUPVd4Lj/8hgYuVH44vG1P 0y+adPcYfzXjpikKrEzv3NDcohSxmXsbMfg8BV1f35sC X-Google-Smtp-Source: AKy350ac33ueQheEYkz7wtwClwW8y30g8Pu0POn8LSq55BDwGEtalrhu1EoIAntXw3vGid4sd2GNWhDKrHEgwMIK9HA= X-Received: by 2002:a05:6402:331:b0:502:23a2:6739 with SMTP id q17-20020a056402033100b0050223a26739mr12345295edw.28.1682361265068; Mon, 24 Apr 2023 11:34:25 -0700 (PDT) MIME-Version: 1.0 References: <20230424050329.1501348-1-goldstein.w.n@gmail.com> In-Reply-To: From: Noah Goldstein Date: Mon, 24 Apr 2023 13:34:13 -0500 Message-ID: Subject: Re: [PATCH v1] x86: Increase `non_temporal_threshold` to roughly `sizeof_L3 / 2` To: "H.J. Lu" Cc: libc-alpha@sourceware.org, carlos@systemhalted.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Apr 24, 2023 at 1:10=E2=80=AFPM H.J. Lu wrote= : > > On Sun, Apr 23, 2023 at 10:03=E2=80=AFPM Noah Goldstein wrote: > > > > Current `non_temporal_threshold` set to roughly '3/4 * sizeof_L3 / > > ncores_per_socket'. This patch updates that value to roughly > > 'sizeof_L3 / 2` > > > > The original value (specifically dividing the `ncores_per_socket`) was > > done to limit the amount of other threads' data a `memcpy`/`memset` > > could evict. > > > > Dividing by 'ncores_per_socket', however leads to exceedingly low > > non-temporal threshholds and leads to using non-temporal stores in > > cases where `rep movsb` is multiple times faster. > > > > Furthermore, non-temporal stores are written directly to disk so using > > Why is "disk" here? I mean main-memory. Will update in V2. > > > it at a size much smaller than L3 can place soon to be accessed data > > much further away than it otherwise could be. As well, modern machines > > are able to detect streaming patterns (especially if `rep movsb` is > > used) and provide LRU hints to the memory subsystem. This in affect > > caps the total amount of eviction at 1/cache_assosiativity, far below > > meaningfully thrashing the entire cache. > > > > As best I can tell, the benchmarks that lead this small threshold > > where done comparing non-temporal stores versus standard cacheable > > stores. A better comparison (linked below) is to be `rep movsb` which, > > on the measure systems, is nearly 2x faster than non-temporal stores > > at the low-end of the previous threshold, and within 10% for over > > 100MB copies (well past even the current threshold). In cases with a > > low number of threads competing for bandwidth, `rep movsb` is ~2x > > faster up to `sizeof_L3`. > > > > Should we limit it to processors with ERMS (Enhanced REP MOVSB/STOSB)? > Think that would probably make sense. We see more meaningful regression for larger sizes when using standard store loop. Think /nthreads is still too small. How about if ERMS: L3/2 else: L3 / (2 * sqrt(nthreads)) ? > > Benchmarks comparing non-temporal stores, rep movsb, and cacheable > > stores where done using: > > https://github.com/goldsteinn/memcpy-nt-benchmarks > > > > Sheets results (also available in pdf on the github): > > https://docs.google.com/spreadsheets/d/e/2PACX-1vS183r0rW_jRX6tG_E90m9q= VuFiMbRIJvi5VAE8yYOvEOIEEc3aSNuEsrFbuXw5c3nGboxMmrupZD7K/pubhtml > > --- > > sysdeps/x86/dl-cacheinfo.h | 35 ++++++++++++++--------------------- > > 1 file changed, 14 insertions(+), 21 deletions(-) > > > > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > > index ec88945b39..f25309dbc8 100644 > > --- a/sysdeps/x86/dl-cacheinfo.h > > +++ b/sysdeps/x86/dl-cacheinfo.h > > @@ -604,20 +604,11 @@ intel_bug_no_cache_info: > > =3D ((cpu_features->features[CPUID_INDEX_1].cpuid.ebx >> 1= 6) > > & 0xff); > > } > > - > > - /* Cap usage of highest cache level to the number of supported > > - threads. */ > > - if (shared > 0 && threads > 0) > > - shared /=3D threads; > > } > > > > /* Account for non-inclusive L2 and L3 caches. */ > > if (!inclusive_cache) > > - { > > - if (threads_l2 > 0) > > - core /=3D threads_l2; > > - shared +=3D core; > > - } > > + shared +=3D core; > > > > *shared_ptr =3D shared; > > *threads_ptr =3D threads; > > @@ -730,17 +721,19 @@ dl_init_cacheinfo (struct cpu_features *cpu_featu= res) > > cpu_features->level3_cache_linesize =3D level3_cache_linesize; > > cpu_features->level4_cache_size =3D level4_cache_size; > > > > - /* The default setting for the non_temporal threshold is 3/4 of one > > - thread's share of the chip's cache. For most Intel and AMD proces= sors > > - with an initial release date between 2017 and 2020, a thread's ty= pical > > - share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 > > - threshold leaves 125 KBytes to 500 KBytes of the thread's data > > - in cache after a maximum temporal copy, which will maintain > > - in cache a reasonable portion of the thread's stack and other > > - active data. If the threshold is set higher than one thread's > > - share of the cache, it has a substantial risk of negatively > > - impacting the performance of other threads running on the chip. *= / > > - unsigned long int non_temporal_threshold =3D shared * 3 / 4; > > + /* The default setting for the non_temporal threshold is 1/2 of size > > + of chip's cache. For most Intel and AMD processors with an > > + initial release date between 2017 and 2023, a thread's typical > > + share of the cache is from 18-64MB. Using the 1/2 L3 is meant to > > + estimate the point where non-temporal stores begin outcompeting > > + other methods. As well the point where the fact that non-temporal > > + stores are forced back to disk would already occured to the > > + majority of the lines in the copy. Note, concerns about the > > + entire L3 cache being evicted by the copy are mostly alleviated > > + by the fact that modern HW detects streaming patterns and > > + provides proper LRU hints so that the the maximum thrashing > > + capped at 1/assosiativity. */ > > + unsigned long int non_temporal_threshold =3D shared / 2; > > /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the= value of > > 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it= is best > > if that operation cannot overflow. Minimum of 0x4040 (16448) beca= use the > > -- > > 2.34.1 > > > > > -- > H.J.