From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by sourceware.org (Postfix) with ESMTPS id 745253858D35 for ; Thu, 17 Aug 2023 16:37:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 745253858D35 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=google.com Received: by mail-qk1-x736.google.com with SMTP id af79cd13be357-76d7fcb2c62so631285a.1 for ; Thu, 17 Aug 2023 09:37:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692290256; x=1692895056; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=rAg4Ix9ZS0WHooVrRNNZ45su6HCFzTmMW7cGBCcqFdY=; b=GQYGb7tSsjC0RUcl2ypo5sz77bMRVNdOLHF9hEzlnoXAcyMzPa/ctPdPOMMsXv+QZl A8iUuaoD8c0sxadl5IPV0cNCZDtcrLSEEWJeanwt4TYdXZXjOzgry8Oo3wQrlZHO7nBp 2p4xzAj9org8tY4DoQkAeuy4aDFGikppgPDm55RDB3VBpiLQODzIfK+K3/wdXN7OnfCp NmvvEKOQccRe1l9y2n2Ln6TT5iz360q2GIvGi2Kn7q+AtnXyqQmPecSDX4aKqjP1Q73A 2BqvLZHCF9gi+PAP7WlvRv1MvX8AqG+H8HiWptvluPhJfvyPQBXkk2uxf+8oL4q/bUzR ftBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692290256; x=1692895056; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rAg4Ix9ZS0WHooVrRNNZ45su6HCFzTmMW7cGBCcqFdY=; b=aUTLm76//fjhqaF41mnuTQhdnful36IrQZ1CPK94r4H9bMYVhEBKNU9Tck5JdVKUdI RkyOLEIe0TaGGJRcNebX/rkx/7pFr8QzMDOtdRiQ/6MOMbXidRYIjAmH3GU+GNTQtxKM YnOF+yfq+KlGtoFoQw/PJd+GpBVNJqWS0qNxzd1txqPs5WmOYu+xtxPKspZU545RdW8R fx6IC3Avv7MQ26t03iw29KTySFrgclfgJuhIXu/MDYdIC5fms+A9CPEljTo+sTro/rwY 5imoOj/59YpeQSvzylfE26+8+3hYe6FtT0MVTVgj+dPZ1VLovoXDsNtyciDZ9+wZDSBx z+7w== X-Gm-Message-State: AOJu0YxpeKH3o0NZnk+B8Iqa9Th2B50i8l3bKsH9auMoqICguZrKugvY AOTCqVYdBdIP781h9QKujnYKmGNjdl9cqfm/4DDkig== X-Google-Smtp-Source: AGHT+IGqp3hdL7b7sn9gPanQD44gYGRIjHjyB9kbKiFOGWxGHPR5NhTMFWCgIDiKA12xCtJ3nxaYVgI8iux17t2H+go= X-Received: by 2002:a05:620a:2a0a:b0:767:1d7e:ec3d with SMTP id o10-20020a05620a2a0a00b007671d7eec3dmr4545538qkp.2.1692290255455; Thu, 17 Aug 2023 09:37:35 -0700 (PDT) MIME-Version: 1.0 References: <20230802155903.2552780-1-evan@rivosinc.com> <20230802155903.2552780-6-evan@rivosinc.com> <87il9w37vi.fsf@oldenburg.str.redhat.com> <6f0911c6-b24b-444c-4b4b-a62e49a51734@linaro.org> <548fc7d5-6225-69e7-f4a7-47669d2fdbd5@linaro.org> In-Reply-To: From: enh Date: Thu, 17 Aug 2023 09:37:23 -0700 Message-ID: Subject: Re: [PATCH v6 5/5] riscv: Add and use alignment-ignorant memcpy To: Evan Green Cc: Richard Henderson , Florian Weimer , libc-alpha@sourceware.org, slewis@rivosinc.com, palmer@rivosinc.com, vineetg@rivosinc.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-17.7 required=5.0 tests=BAYES_00,DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,ENV_AND_HDR_SPF_MATCH,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,USER_IN_DEF_DKIM_WL,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Aug 17, 2023 at 9:27=E2=80=AFAM Evan Green wrot= e: > > On Wed, Aug 16, 2023 at 4:18=E2=80=AFPM enh wrote: > > > > On Tue, Aug 15, 2023 at 4:02=E2=80=AFPM Evan Green = wrote: > > > > > > On Tue, Aug 15, 2023 at 2:54=E2=80=AFPM enh wrote: > > > > > > > > On Tue, Aug 15, 2023 at 9:41=E2=80=AFAM Evan Green wrote: > > > > > > > > > > On Fri, Aug 11, 2023 at 5:01=E2=80=AFPM enh wrot= e: > > > > > > > > > > > > On Mon, Aug 7, 2023 at 5:01=E2=80=AFPM Evan Green wrote: > > > > > > > > > > > > > > On Mon, Aug 7, 2023 at 3:48=E2=80=AFPM enh w= rote: > > > > > > > > > > > > > > > > On Mon, Aug 7, 2023 at 3:11=E2=80=AFPM Evan Green wrote: > > > > > > > > > > > > > > > > > > On Thu, Aug 3, 2023 at 3:30=E2=80=AFPM Richard Henderson > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > On 8/3/23 11:42, Evan Green wrote: > > > > > > > > > > > On Thu, Aug 3, 2023 at 10:50=E2=80=AFAM Richard Hende= rson > > > > > > > > > > > wrote: > > > > > > > > > > >> Outside libc something is required. > > > > > > > > > > >> > > > > > > > > > > >> An extra parameter to ifunc is surprising though, an= d clearly not ideal per the extra > > > > > > > > > > >> hoops above. I would hope for something with hidden= visibility in libc_nonshared.a that > > > > > > > > > > >> could always be called directly. > > > > > > > > > > > > > > > > > > > > > > My previous spin took that approach, defining a > > > > > > > > > > > __riscv_hwprobe_early() in libc_nonshared that could = route to the real > > > > > > > > > > > function if available, or make the syscall directly i= f not. But that > > > > > > > > > > > approach had the drawback that ifunc users couldn't t= ake advantage of > > > > > > > > > > > the vDSO, and then all users had to comprehend the di= fference between > > > > > > > > > > > __riscv_hwprobe() and __riscv_hwprobe_early(). > > > > > > > > > > > > > > > > > > > > I would define __riscv_hwprobe such that it could take = advantage of the vDSO once > > > > > > > > > > initialization reaches a certain point, but cope with b= eing run earlier than that point by > > > > > > > > > > falling back to the syscall. > > > > > > > > > > > > > > > > > > > > That constrains the implementation, I guess, in that it= can't set errno, but just > > > > > > > > > > returning the negative errno from the syscall seems fin= e. > > > > > > > > > > > > > > > > > > > > It might be tricky to get a reference to GLRO(dl_vdso_r= iscv_hwprobe) very early, but I > > > > > > > > > > would hope that some application of __attribute__((weak= )) might correctly get you a NULL > > > > > > > > > > prior to full relocations being complete. > > > > > > > > > > > > > > > > > > Right, this is what we had in the previous iteration of t= his series, > > > > > > > > > and it did work ok. But it wasn't as good since it meant = ifunc > > > > > > > > > selectors always got stuck in the null/fallback case and = were forced > > > > > > > > > to make the syscall. With this mechanism they get to take= advantage of > > > > > > > > > the vDSO. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > In contrast, IMO this approach is much nicer. Ifunc w= riters are > > > > > > > > > > > already used to getting hwcap info via a parameter. A= dding this second > > > > > > > > > > > parameter, which also provides hwcap-like things, see= ms like a natural > > > > > > > > > > > extension. I didn't quite follow what you meant by th= e "extra hoops > > > > > > > > > > > above". > > > > > > > > > > > > > > > > > > > > The check for null function pointer, for sure. But als= o consider how __riscv_hwprobe is > > > > > > > > > > going to be used. > > > > > > > > > > > > > > > > > > > > It might be worth defining some helper functions for pr= obing a single key or a single > > > > > > > > > > field. E.g. > > > > > > > > > > > > > > > > > > > > uint64_t __riscv_hwprobe_one_key(int64_t key, unsigned = int flags) > > > > > > > > > > { > > > > > > > > > > struct riscv_hwprobe pair =3D { .key =3D key }; > > > > > > > > > > int err =3D __riscv_hwprobe(&pair, 1, 0, NULL, flags= ); > > > > > > > > > > if (err) > > > > > > > > > > return err; > > > > > > > > > > if (pair.key =3D=3D -1) > > > > > > > > > > return -ENOENT; > > > > > > > > > > return pair.value; > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > This implementation requires that no future hwprobe key= define a value which as a valid > > > > > > > > > > value in the errno range (or better, bit 63 unused). A= lternately, or additionally: > > > > > > > > > > > > > > > > > > > > bool __riscv_hwprobe_one_mask(int64_t key, uint64_t mas= k, uint64_t val, int flags) > > > > > > > > > > { > > > > > > > > > > struct riscv_hwprobe pair =3D { .key =3D key }; > > > > > > > > > > return (__riscv_hwprobe(&pair, 1, 0, NULL, flags) = =3D=3D 0 > > > > > > > > > > && pair.key !=3D -1 > > > > > > > > > > && (pair.value & mask) =3D=3D val); > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > These yield either > > > > > > > > > > > > > > > > > > > > int64_t v =3D __riscv_hwprobe_one_key(CPUPERF_0, 0= ); > > > > > > > > > > if (v >=3D 0 && (v & MISALIGNED_MASK) =3D=3D MISAL= IGNED_FAST) > > > > > > > > > > return __memcpy_noalignment; > > > > > > > > > > return __memcpy_generic; > > > > > > > > > > > > > > > > > > > > or > > > > > > > > > > > > > > > > > > > > if (__riscv_hwprobe_one_mask(CPUPERF_0, MISALIGNED= _MASK, MISALIGNED_FAST, 0)) > > > > > > > > > > return __memcpy_noalignment; > > > > > > > > > > return __memcpy_generic; > > > > > > > > > > > > > > > > > > > > which to my mind looks much better for a pattern you'll= be replicating so very many times > > > > > > > > > > across all of the ifunc implementations in the system. > > > > > > > > > > > > > > > > > > Ah, I see. I could make a static inline function in the h= eader that > > > > > > > > > looks something like this (mangled by gmail, sorry): > > > > > > > > > > > > > > > > > > /* Helper function usable from ifunc selectors that probe= s a single key. */ > > > > > > > > > static inline int __riscv_hwprobe_one(__riscv_hwprobe_t h= wprobe_func, > > > > > > > > > signed long long int key, > > > > > > > > > unsigned long long int *value) > > > > > > > > > { > > > > > > > > > struct riscv_hwprobe pair; > > > > > > > > > int rc; > > > > > > > > > > > > > > > > > > if (!hwprobe_func) > > > > > > > > > return -ENOSYS; > > > > > > > > > > > > > > > > > > pair.key =3D key; > > > > > > > > > rc =3D hwprobe_func(&pair, 1, 0, NULL, 0); > > > > > > > > > if (rc) { > > > > > > > > > return rc; > > > > > > > > > } > > > > > > > > > > > > > > > > > > if (pair.key < 0) { > > > > > > > > > return -ENOENT; > > > > > > > > > } > > > > > > > > > > > > > > > > > > *value =3D pair.value; > > > > > > > > > return 0; > > > > > > > > > } > > > > > > > > > > > > > > > > > > The ifunc selector would then be significantly cleaned up= , looking > > > > > > > > > something like: > > > > > > > > > > > > > > > > > > if (__riscv_hwprobe_one(hwprobe_func, RISCV_HWPROBE_KEY_C= PUPERF_0, &value)) > > > > > > > > > return __memcpy_generic; > > > > > > > > > > > > > > > > > > if (value & RISCV_HWPROBE_MISALIGNED_MASK) =3D=3D RISCV_H= WPROBE_MISALIGNED_FAST) > > > > > > > > > return __memcpy_noalignment; > > > > > > > > > > > > > > > > (Android's libc maintainer here, having joined the list jus= t to talk > > > > > > > > about risc-v ifuncs :-) ) > > > > > > > > > > > > > > > > has anyone thought about calling ifunc resolvers more like = this... > > > > > > > > > > > > > > > > --same part of the dynamic loader that caches the two getau= xval()s for arm64-- > > > > > > > > static struct riscv_hwprobe probes[] =3D { > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_MVENDORID}, > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_MARCHID}, > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_MIMPID}, > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_BASE_BEHAVIOR}, > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_IMA_EXT}, > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_CPUPERF_0}, > > > > > > > > ... // every time a new key is added to the kernel, we add = it here > > > > > > > > }; > > > > > > > > __riscv_hwprobe(...); // called once > > > > > > > > > > > > > > > > --part of the dynamic loader that calls ifunc resolvers-- > > > > > > > > (*ifunc_resolver)(sizeof(probes)/sizeof(probes[0]), probes)= ; > > > > > > > > > > > > > > > > this is similar to what we already have for arm64 (where th= ere's a > > > > > > > > getauxval(AT_HWCAP) and a pointer to a struct for AT_HWCAP2= and > > > > > > > > potentially others), but more uniform, and avoiding the sou= rce > > > > > > > > (in)compatibility issues of adding new fields to a struct [= even if it > > > > > > > > does have a size_t to "version" it like the arm64 ifunc str= uct]. > > > > > > > > > > > > > > > > yes, it means everyone pays to get all the hwprobes, but th= at gets > > > > > > > > amortized. and lookup in the ifunc resolver is simple and q= uick. if we > > > > > > > > know that the keys will be kept dense, we can even have cod= e in ifunc > > > > > > > > resolvers like > > > > > > > > > > > > > > > > if (probes[RISCV_HWPROBE_BASE_BEHAVIOR_IMA].value & RISCV_H= WPROBE_IMA_V) ... > > > > > > > > > > > > > > > > though personally for the "big ticket items" that get a let= ter to > > > > > > > > themselves like V, i'd be tempted to pass `(getauxval(AT_HW= CAP), > > > > > > > > probe_count, probes_ptr)` to the resolver, but i hear that'= s > > > > > > > > controversial :-) > > > > > > > > > > > > > > Hello, welcome to the fun! :) > > > > > > > > > > > > (sorry for the delay. i've been thinking :-) ) > > > > > > > > > > > > > What you're describing here is almost exactly what we did ins= ide the > > > > > > > vDSO function. The vDSO function acts as a front for a handfu= l of > > > > > > > probe values that we've already completed and cached in users= pace. We > > > > > > > opted to make it a function, rather than exposing the data it= self via > > > > > > > vDSO, so that we had future flexibility in what elements we c= ached in > > > > > > > userspace and their storage format. We can update the kernel = as needed > > > > > > > to cache the hottest things in userspace, even if that means > > > > > > > rearranging the data format, passing through some extra infor= mation, > > > > > > > or adding an extra snip of code. My hope is callers can direc= tly > > > > > > > interact with the vDSO function (though maybe as Richard sugg= ested > > > > > > > maybe with the help of a tidy inline helper), rather than try= ing to > > > > > > > add a second layer of userspace caching. > > > > > > > > > > > > on reflection i think i might be too focused on the FMV use cas= e, in > > > > > > part because we're looking at those compiler-generated ifuncs f= or > > > > > > arm64 on Android atm. i think i'm imagining a world where there= 's a > > > > > > lot of that, and worrying about having to pay for the setup, ca= ll, and > > > > > > loop for each ifunc, and wondering why we don't just pay once i= nstead. > > > > > > (as a bit of background context, Android "app" start is actuall= y a > > > > > > dlopen() in a clone of an existing zygote process, and in gener= al app > > > > > > launch time is one of the key metrics anyone who's serious is > > > > > > optimizing for. you'd be surprised how much of my life i spend > > > > > > explaining to people that if they want dlopen() to be faster, m= aybe > > > > > > they shouldn't ask us to run thousands of ELF constructors.) > > > > > > > > > > > > but... the more time i spend looking at what we actually need i= n > > > > > > third-party open source libraries right now i realize that libc= and > > > > > > FMV (which is still a future thing for us anyway) are really th= e only > > > > > > _actual_ ifunc users. perhaps in part because macOS/iOS don't h= ave > > > > > > ifuncs, all the libraries that are part of the OS itself, for e= xample, > > > > > > are just doing their own thing with function pointers and > > > > > > pthread_once() or whatever. > > > > > > > > > > > > (i have yet to try to get any data on actual apps. i have no re= ason to > > > > > > think they'll be very different, but that could easily be skewe= d by > > > > > > popular middleware or a popular game engine using ifuncs, so i = do plan > > > > > > on following up on that.) > > > > > > > > > > > > "how do they decide what to set that function pointer to?". wel= l, it > > > > > > looks like in most cases cpuid on x86 and calls to getauxval() > > > > > > everywhere else. in some cases that's actually via some other l= ibrary: > > > > > > https://github.com/pytorch/cpuinfo or > > > > > > https://github.com/google/cpu_features for example. so they hav= e a > > > > > > layer of caching there, even in cases where they don't have a s= ingle > > > > > > function that sets all the function pointers. > > > > > > > > > > Right, function multi-versioning is just the sort of spot where w= e'd > > > > > imagine hwprobe gets used, since it's providing similar/equivalen= t > > > > > information to what cpuid does on x86. It may not be quite as fas= t as > > > > > cpuid (I don't know how fast cpuid actually is). But with the vDS= O > > > > > function+data in userspace it should be able to match getauxval()= in > > > > > performance, as they're both a function pointer plus a loop. We'r= e > > > > > sort of planning for a world in which RISC-V has a wider set of t= hese > > > > > values to fetch, such that a ifunc selector may need a more compl= ex > > > > > set of information. Hwprobe and the vDSO gives us the ability bot= h to > > > > > answer multiple queries fast, and freely allocate more keys that = may > > > > > represent versioned features or even compound features. > > > > > > > > yeah, my incorrect mental model was that -- primarily because of > > > > x86-64 and cpuid -- every function would get its own ifunc resolver > > > > that would have to make a query. but the [in progress] arm64 > > > > implementation shows that that's not really the case anyway, and we > > > > can just cache __riscv_hwprobe() in the same [one] place that > > > > getauxval() is already being cached for arm64. > > > > > > Sounds good. > > > > > > > > > > > > > so assuming i don't find that apps look very different from the= OS > > > > > > (that is: that apps use lots of ifuncs), i probably don't care = at all > > > > > > until we get to FMV. and i probably don't care for FMV, because > > > > > > compiler-rt (or gcc's equivalent) will be the "caching layer" t= here. > > > > > > (and on Android it'll be a while before i have to worry about l= ibc's > > > > > > ifuncs because we'll require V and not use ifuncs there for the > > > > > > foreseeable future.) > > > > > > > > > > > > so, yeah, given that i've adopted the "pass a null pointer rath= er than > > > > > > no arguments" convention you have, we have room for expansion i= f/when > > > > > > FMV is a big thing, and until then -- unless i'm shocked by wha= t i > > > > > > find looking at actual apps -- i don't think i have any reason = to > > > > > > believe that ifuncs matter that much, and if compiler-rt makes = one > > > > > > __riscv_hwprobe() call per .so, that's probably fine. (i alread= y spend > > > > > > a big chunk of my life advising people to just have one .so fil= e, > > > > > > exporting nothing but a JNI_OnLoad symbol, so this will just ma= ke that > > > > > > advice even better advice :-) ) > > > > > > > > > > Just to confirm, by "pass a null pointer", you're saying that the > > > > > Android libc also passes NULL as the second ifunc selector argume= nt > > > > > (or first)? > > > > > > > > #elif defined(__riscv) > > > > // This argument and its value is just a placeholder for now, > > > > // but it means that if we do pass something in future (such as > > > > // getauxval() and/or hwprobe key/value pairs), callees will be a= ble to > > > > // recognize what they're being given. > > > > typedef ElfW(Addr) (*ifunc_resolver_t)(void*); > > > > return reinterpret_cast(resolver_addr)(nullptr)= ; > > > > > > > > it's arm64 that has the initial getauxval() argument: > > > > > > > > #if defined(__aarch64__) > > > > typedef ElfW(Addr) (*ifunc_resolver_t)(uint64_t, __ifunc_arg_t*); > > > > static __ifunc_arg_t arg; > > > > static bool initialized =3D false; > > > > if (!initialized) { > > > > initialized =3D true; > > > > arg._size =3D sizeof(__ifunc_arg_t); > > > > arg._hwcap =3D getauxval(AT_HWCAP); > > > > arg._hwcap2 =3D getauxval(AT_HWCAP2); > > > > } > > > > return reinterpret_cast(resolver_addr)(arg._hwc= ap > > > > | _IFUNC_ARG_HWCAP, &arg); > > > > > > > > https://android.googlesource.com/platform/bionic/+/main/libc/bionic= /bionic_call_ifunc_resolver.cpp > > > > > > > > > That's good. It sounds like you're planning to just > > > > > continue passing NULL for now, and wait for people to start clamo= ring > > > > > for this in android libc? > > > > > > > > yeah, and i'm assuming there will never be any clamor ... yesterday > > > > and today i actually checked a bunch of popular apks, and didn't fi= nd > > > > any that were currently using ifuncs. > > > > > > > > the only change i'm thinking of making right now is that "there's a > > > > single argument, and it's null" should probably be the default. > > > > obviously since Android doesn't add new architectures very often, t= his > > > > is only likely to affect x86/x86-64 for the foreseeable future, but > > > > being able to recognize at a glance "am i running under a libc new > > > > enough to pass me arguments?" would certainly have helped for arm64= . > > > > even if x86/x86-64 never benefit, it seems like the right default f= or > > > > the #else clause... > > > > > > Sounds good, thanks for the pointers. The paranoid person in me would > > > also add a comment in the risc-v section that if a pointer to hwprobe > > > is added, it should be added as the second argument, behind hwcap as > > > the first (assuming this change lands). > > > > > > Come to think of it, the static inline helper I'm proposing in my > > > discussion with Richard needs to take both arguments, since callers > > > need to check both ((arg1 !=3D 0) && (arg2 !=3D NULL)) to safely know= that > > > arg2 is a pointer to __riscv_hwprobe(). > > > > presumably not `(arg1 !=3D 0)` but `(arg1 & _IFUNC_ARG_HWCAP)` to match= arm64? > > It looks like we didn't do that _IFUNC_ARG_HWCAP bit on riscv. > Actually, looking at the history of sysdeps/riscv/dl-irel.h, hwcap has > always been passed as the first argument. So I think I don't need to > check it in the (glibc-specific) inline helper function, I can safely > assume it's there and go straight to checking the second argument. oh i misunderstood what you were saying earlier. > If you were coding this directly in a library or application, you > would need to check the first arg to be compatible with other libcs > like Android's. we haven't shipped yet, so if you're telling me glibc is passing `(getauxval(AT_HWCAP), nullptr)`, i'll change bionic to do the same today ... the whole reason i'm here on this thread is to ensure source compatibility for anyone writing ifuncs :-) > I think checking against zero should be ok since bits > like I, M, A should always be set. (I didn't dig through the kernel > history, so maybe not on really old kernels? But you're not going to > get hwprobe on those anyway either so the false bailout is correct). > > -Evan