From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) by sourceware.org (Postfix) with ESMTPS id E3CE43857C59 for ; Thu, 20 May 2021 21:23:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E3CE43857C59 Received: by mail-ej1-f46.google.com with SMTP id z12so26018230ejw.0 for ; Thu, 20 May 2021 14:23:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6QZCjGGQzo62kjW+htbxsvDcnxh1XkGFFLyzifku0P8=; b=Iqo3WNgihRSTpRJ7lw2AUwH1PuL/WkTa5r1w16MEQOWuQUKE4GR06E7Fg844WHstku YNr3ckzakuGiBnyZr5A5TbWp7g7hvUI8I4juAmx/WxBEfJE6Dw8pZq+P4lPjiXPFLoe/ K0j7zoTOT4Ust4PwO/PHhtco2icWjgWUXdLUBuL5I8x8lhudjIqQq1V6dzAZLBwq4M87 t090xn8jXLkad0iytU82JVgRZiIYCsuHEql4G/U4qjk+uyb7IN/lYSnQyRm+irm8RcAY 1aUJLS1v+8guZwcd2pjmCK42xYLfXHyoWJQ+SX536HlqOdwLW3hpUIJWxHUch+QOb6nd OSgw== X-Gm-Message-State: AOAM5302t5nHTCFOLAWLWSmAbDQA+eUKVkwSFjEBCPRsq4aV+G36ppKb eb/hHvLg+idVhcd+1wW/Ig+9aMt4Jmk/NIQcBDc= X-Google-Smtp-Source: ABdhPJxTYpFsr6+PpLb8DlYBOxH+GMFJU1dlizi414eWaC07eXoiSXEJYZ5LuZscjGALK/3kDYFRGqthncH+EjXUGyA= X-Received: by 2002:a17:906:2dca:: with SMTP id h10mr6480711eji.507.1621545789994; Thu, 20 May 2021 14:23:09 -0700 (PDT) MIME-Version: 1.0 References: <20210415044258.GA6318@zn.tnic> <20210415052938.GA2325@1wt.eu> <20210415054713.GB6318@zn.tnic> <20210419141454.GE9093@zn.tnic> <20210419191539.GH9093@zn.tnic> <20210419215809.GJ9093@zn.tnic> <874kf11yoz.ffs@nanos.tec.linutronix.de> <87k0ntazyn.ffs@nanos.tec.linutronix.de> In-Reply-To: <87k0ntazyn.ffs@nanos.tec.linutronix.de> From: Len Brown Date: Thu, 20 May 2021 17:22:58 -0400 Message-ID: Subject: Re: Candidate Linux ABI for Intel AMX and hypothetical new related features To: Thomas Gleixner Cc: Borislav Petkov , Willy Tarreau , Andy Lutomirski , Florian Weimer , "Bae, Chang Seok" , Dave Hansen , X86 ML , LKML , Linux API , "libc-alpha@sourceware.org" , Rich Felker , Kyle Huey , Keno Fischer , Arjan van de Ven Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 May 2021 21:23:12 -0000 On Thu, May 20, 2021 at 4:54 PM Thomas Gleixner wrote: Thomas, > > AMX is analogous to the multiplier used by AVX-512. > > The architectural state must exist on every CPU, including HT siblings. > > Today, the HT siblings share the same execution unit, > > and I have no reason to expect that will change. > > I'm well aware that HT siblings share the same execution unit for > AVX. > > Though AMX is if I remember the discussions two years ago correctly > shared by more than the HT siblings which makes things worse. I regret that we were unable to get together in the last year to have an updated discussion. I think if we had, then we would have saved a lot of mis-understanding and a lot of email! So let me emphasize here: There is one TMUL execution unit per core. It is shared by the HT siblings within that core. So the comparison to the AVX-512 multiplier is a good one. Len Brown, Intel Open Source Technology Center