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From: Andy Lutomirski <luto@kernel.org>
Date: Fri, 16 Apr 2021 15:03:39 -0700
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Subject: Re: Candidate Linux ABI for Intel AMX and hypothetical new related
 features
To: Len Brown <lenb@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>, Willy Tarreau <w@1wt.eu>,
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On Fri, Apr 16, 2021 at 2:54 PM Len Brown <lenb@kernel.org> wrote:
>
> On Thu, Apr 15, 2021 at 12:24 PM Andy Lutomirski <luto@kernel.org> wrote:
> > On Wed, Apr 14, 2021 at 2:48 PM Len Brown <lenb@kernel.org> wrote:
>
> > > > ... the transition penalty into and out of AMX code
>
> The concept of 'transition' exists between AVX and SSE instructions
> because it is possible to mix both instruction sets and touch different
> parts of the same registers.  The "unused" parts of those registers
> need to be tracked to assure that data is not lost when mixing.

I get it.  That does not explain why LDMXCSR and VLDMXCSR cause
pipelines stalls.

>
> This concept is moot with AMX, which has its own dedicated registers.
>
> > What is the actual impact of a trivial function that initializes the
> > tile config, does one tiny math op, and then does TILERELEASE?


^^^^ "does one tiny math op"


AVX-512 *also* has sort-of-dedicated registers: ZMM16 and up.  I still
can't find any conclusive evidence as to whether that avoids the
performance hit.

Intel's track record at actually explaining what operations cause what
particular performance disasters is poor, and your explanation is not
helping the situation.  Sorry.