From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by sourceware.org (Postfix) with ESMTPS id 232E8385483C for ; Thu, 17 Aug 2023 17:41:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 232E8385483C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4ff8cf11b90so4343092e87.1 for ; Thu, 17 Aug 2023 10:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1692294086; x=1692898886; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=jxN0u2xKUGBG1HMwV+ByaYRaqxg8izQp749dRZrgF2s=; b=qLE6kIBx5jHT3Am3lyrJjcT2EOfghGzkLtU1NBhEsQwOLPj4t5DW3ZBmaB0RmMbS9+ 6m120Xx4ji228dQnuRxgTIs/oHq/M9eoSynXPHrt/I9ASCZ1XSqEznTqAU/AMk9iIj4G oS1/i1ugFYzyuAYT+LF7oxQdbu/wUXZSaYyJm30i71f5fi/8XcxYUvuOMS7f+cEiCPTL SC35j0xHasZsRk4Bl6+bKZG2pbjRg86Ha7WdsVTBle5mAujc254l6nULrirpgcXY8Sd8 vicIGDM8mOKh6a19djZrHvh6MyVLSObwiaJ7fhiim2mt9qfWH5+aBkIh2jrIH+jzhAHT DgRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692294086; x=1692898886; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jxN0u2xKUGBG1HMwV+ByaYRaqxg8izQp749dRZrgF2s=; b=Y05HCHwdkr/c96zhz4j06fymTDI1UVh4NMPnBrkqFmb/tTVQXxAPfQetIRpRZMuUIf qzs9L+uuSG2ERpob4oA5yW5DnwIGvvaqT3VvGPxHDZDvCAv+9CNESXOOkfyTHjjMcKat hc1KqQhxOhQddjpcwrb/sHIutdiP8Ux9BvIyyHzrdjhw0qDhO+JcG1FB/c/GR932rBt3 lD+eIyJ66OW3eNoFS+5aGaqC8j0nvJRAimHJzJRQBinQb7ZvglIWG+OEhgP+TuFHeoRb 7OIbF4MKESJtTjVmGRNJzYJZnSt9NqGAPQovkGaomjmAvh01HcNOVHc997+sKC86KM6q 37QA== X-Gm-Message-State: AOJu0Yw/pe2dF0WO6dM+1F6isMJKNG7bYJ1zpfmphis1KyQT9F815mkK wNhv2dao+au4ndrLYVsJg6QtoE3zr4RBLqCNjqqaLw== X-Google-Smtp-Source: AGHT+IH4UNeu6xwbcGfCM/Z+1/msft6HMoMlu/B8j2m3rWHUCcHgj4yROBoe1XDdJXDhYiQct7Ib5zxLx5DfbpeUbzw= X-Received: by 2002:a05:6512:4016:b0:4f8:70d8:28f8 with SMTP id br22-20020a056512401600b004f870d828f8mr6627297lfb.55.1692294086404; Thu, 17 Aug 2023 10:41:26 -0700 (PDT) MIME-Version: 1.0 References: <20230802155903.2552780-1-evan@rivosinc.com> <20230802155903.2552780-6-evan@rivosinc.com> <87il9w37vi.fsf@oldenburg.str.redhat.com> <6f0911c6-b24b-444c-4b4b-a62e49a51734@linaro.org> <548fc7d5-6225-69e7-f4a7-47669d2fdbd5@linaro.org> In-Reply-To: From: Evan Green Date: Thu, 17 Aug 2023 10:40:50 -0700 Message-ID: Subject: Re: [PATCH v6 5/5] riscv: Add and use alignment-ignorant memcpy To: enh Cc: Richard Henderson , Florian Weimer , libc-alpha@sourceware.org, slewis@rivosinc.com, palmer@rivosinc.com, vineetg@rivosinc.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Aug 17, 2023 at 9:37=E2=80=AFAM enh wrote: > > On Thu, Aug 17, 2023 at 9:27=E2=80=AFAM Evan Green wr= ote: > > > > On Wed, Aug 16, 2023 at 4:18=E2=80=AFPM enh wrote: > > > > > > On Tue, Aug 15, 2023 at 4:02=E2=80=AFPM Evan Green wrote: > > > > > > > > On Tue, Aug 15, 2023 at 2:54=E2=80=AFPM enh wrote: > > > > > > > > > > On Tue, Aug 15, 2023 at 9:41=E2=80=AFAM Evan Green wrote: > > > > > > > > > > > > On Fri, Aug 11, 2023 at 5:01=E2=80=AFPM enh wr= ote: > > > > > > > > > > > > > > On Mon, Aug 7, 2023 at 5:01=E2=80=AFPM Evan Green wrote: > > > > > > > > > > > > > > > > On Mon, Aug 7, 2023 at 3:48=E2=80=AFPM enh = wrote: > > > > > > > > > > > > > > > > > > On Mon, Aug 7, 2023 at 3:11=E2=80=AFPM Evan Green wrote: > > > > > > > > > > > > > > > > > > > > On Thu, Aug 3, 2023 at 3:30=E2=80=AFPM Richard Henderso= n > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > On 8/3/23 11:42, Evan Green wrote: > > > > > > > > > > > > On Thu, Aug 3, 2023 at 10:50=E2=80=AFAM Richard Hen= derson > > > > > > > > > > > > wrote: > > > > > > > > > > > >> Outside libc something is required. > > > > > > > > > > > >> > > > > > > > > > > > >> An extra parameter to ifunc is surprising though, = and clearly not ideal per the extra > > > > > > > > > > > >> hoops above. I would hope for something with hidd= en visibility in libc_nonshared.a that > > > > > > > > > > > >> could always be called directly. > > > > > > > > > > > > > > > > > > > > > > > > My previous spin took that approach, defining a > > > > > > > > > > > > __riscv_hwprobe_early() in libc_nonshared that coul= d route to the real > > > > > > > > > > > > function if available, or make the syscall directly= if not. But that > > > > > > > > > > > > approach had the drawback that ifunc users couldn't= take advantage of > > > > > > > > > > > > the vDSO, and then all users had to comprehend the = difference between > > > > > > > > > > > > __riscv_hwprobe() and __riscv_hwprobe_early(). > > > > > > > > > > > > > > > > > > > > > > I would define __riscv_hwprobe such that it could tak= e advantage of the vDSO once > > > > > > > > > > > initialization reaches a certain point, but cope with= being run earlier than that point by > > > > > > > > > > > falling back to the syscall. > > > > > > > > > > > > > > > > > > > > > > That constrains the implementation, I guess, in that = it can't set errno, but just > > > > > > > > > > > returning the negative errno from the syscall seems f= ine. > > > > > > > > > > > > > > > > > > > > > > It might be tricky to get a reference to GLRO(dl_vdso= _riscv_hwprobe) very early, but I > > > > > > > > > > > would hope that some application of __attribute__((we= ak)) might correctly get you a NULL > > > > > > > > > > > prior to full relocations being complete. > > > > > > > > > > > > > > > > > > > > Right, this is what we had in the previous iteration of= this series, > > > > > > > > > > and it did work ok. But it wasn't as good since it mean= t ifunc > > > > > > > > > > selectors always got stuck in the null/fallback case an= d were forced > > > > > > > > > > to make the syscall. With this mechanism they get to ta= ke advantage of > > > > > > > > > > the vDSO. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > In contrast, IMO this approach is much nicer. Ifunc= writers are > > > > > > > > > > > > already used to getting hwcap info via a parameter.= Adding this second > > > > > > > > > > > > parameter, which also provides hwcap-like things, s= eems like a natural > > > > > > > > > > > > extension. I didn't quite follow what you meant by = the "extra hoops > > > > > > > > > > > > above". > > > > > > > > > > > > > > > > > > > > > > The check for null function pointer, for sure. But a= lso consider how __riscv_hwprobe is > > > > > > > > > > > going to be used. > > > > > > > > > > > > > > > > > > > > > > It might be worth defining some helper functions for = probing a single key or a single > > > > > > > > > > > field. E.g. > > > > > > > > > > > > > > > > > > > > > > uint64_t __riscv_hwprobe_one_key(int64_t key, unsigne= d int flags) > > > > > > > > > > > { > > > > > > > > > > > struct riscv_hwprobe pair =3D { .key =3D key }; > > > > > > > > > > > int err =3D __riscv_hwprobe(&pair, 1, 0, NULL, fla= gs); > > > > > > > > > > > if (err) > > > > > > > > > > > return err; > > > > > > > > > > > if (pair.key =3D=3D -1) > > > > > > > > > > > return -ENOENT; > > > > > > > > > > > return pair.value; > > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > > > This implementation requires that no future hwprobe k= ey define a value which as a valid > > > > > > > > > > > value in the errno range (or better, bit 63 unused). = Alternately, or additionally: > > > > > > > > > > > > > > > > > > > > > > bool __riscv_hwprobe_one_mask(int64_t key, uint64_t m= ask, uint64_t val, int flags) > > > > > > > > > > > { > > > > > > > > > > > struct riscv_hwprobe pair =3D { .key =3D key }; > > > > > > > > > > > return (__riscv_hwprobe(&pair, 1, 0, NULL, flags) = =3D=3D 0 > > > > > > > > > > > && pair.key !=3D -1 > > > > > > > > > > > && (pair.value & mask) =3D=3D val); > > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > > > These yield either > > > > > > > > > > > > > > > > > > > > > > int64_t v =3D __riscv_hwprobe_one_key(CPUPERF_0,= 0); > > > > > > > > > > > if (v >=3D 0 && (v & MISALIGNED_MASK) =3D=3D MIS= ALIGNED_FAST) > > > > > > > > > > > return __memcpy_noalignment; > > > > > > > > > > > return __memcpy_generic; > > > > > > > > > > > > > > > > > > > > > > or > > > > > > > > > > > > > > > > > > > > > > if (__riscv_hwprobe_one_mask(CPUPERF_0, MISALIGN= ED_MASK, MISALIGNED_FAST, 0)) > > > > > > > > > > > return __memcpy_noalignment; > > > > > > > > > > > return __memcpy_generic; > > > > > > > > > > > > > > > > > > > > > > which to my mind looks much better for a pattern you'= ll be replicating so very many times > > > > > > > > > > > across all of the ifunc implementations in the system= . > > > > > > > > > > > > > > > > > > > > Ah, I see. I could make a static inline function in the= header that > > > > > > > > > > looks something like this (mangled by gmail, sorry): > > > > > > > > > > > > > > > > > > > > /* Helper function usable from ifunc selectors that pro= bes a single key. */ > > > > > > > > > > static inline int __riscv_hwprobe_one(__riscv_hwprobe_t= hwprobe_func, > > > > > > > > > > signed long long int key, > > > > > > > > > > unsigned long long int *value) > > > > > > > > > > { > > > > > > > > > > struct riscv_hwprobe pair; > > > > > > > > > > int rc; > > > > > > > > > > > > > > > > > > > > if (!hwprobe_func) > > > > > > > > > > return -ENOSYS; > > > > > > > > > > > > > > > > > > > > pair.key =3D key; > > > > > > > > > > rc =3D hwprobe_func(&pair, 1, 0, NULL, 0); > > > > > > > > > > if (rc) { > > > > > > > > > > return rc; > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > if (pair.key < 0) { > > > > > > > > > > return -ENOENT; > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > *value =3D pair.value; > > > > > > > > > > return 0; > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > The ifunc selector would then be significantly cleaned = up, looking > > > > > > > > > > something like: > > > > > > > > > > > > > > > > > > > > if (__riscv_hwprobe_one(hwprobe_func, RISCV_HWPROBE_KEY= _CPUPERF_0, &value)) > > > > > > > > > > return __memcpy_generic; > > > > > > > > > > > > > > > > > > > > if (value & RISCV_HWPROBE_MISALIGNED_MASK) =3D=3D RISCV= _HWPROBE_MISALIGNED_FAST) > > > > > > > > > > return __memcpy_noalignment; > > > > > > > > > > > > > > > > > > (Android's libc maintainer here, having joined the list j= ust to talk > > > > > > > > > about risc-v ifuncs :-) ) > > > > > > > > > > > > > > > > > > has anyone thought about calling ifunc resolvers more lik= e this... > > > > > > > > > > > > > > > > > > --same part of the dynamic loader that caches the two get= auxval()s for arm64-- > > > > > > > > > static struct riscv_hwprobe probes[] =3D { > > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_MVENDORID}, > > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_MARCHID}, > > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_MIMPID}, > > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_BASE_BEHAVIOR}, > > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_IMA_EXT}, > > > > > > > > > {.value =3D RISCV_HWPROBE_KEY_CPUPERF_0}, > > > > > > > > > ... // every time a new key is added to the kernel, we ad= d it here > > > > > > > > > }; > > > > > > > > > __riscv_hwprobe(...); // called once > > > > > > > > > > > > > > > > > > --part of the dynamic loader that calls ifunc resolvers-- > > > > > > > > > (*ifunc_resolver)(sizeof(probes)/sizeof(probes[0]), probe= s); > > > > > > > > > > > > > > > > > > this is similar to what we already have for arm64 (where = there's a > > > > > > > > > getauxval(AT_HWCAP) and a pointer to a struct for AT_HWCA= P2 and > > > > > > > > > potentially others), but more uniform, and avoiding the s= ource > > > > > > > > > (in)compatibility issues of adding new fields to a struct= [even if it > > > > > > > > > does have a size_t to "version" it like the arm64 ifunc s= truct]. > > > > > > > > > > > > > > > > > > yes, it means everyone pays to get all the hwprobes, but = that gets > > > > > > > > > amortized. and lookup in the ifunc resolver is simple and= quick. if we > > > > > > > > > know that the keys will be kept dense, we can even have c= ode in ifunc > > > > > > > > > resolvers like > > > > > > > > > > > > > > > > > > if (probes[RISCV_HWPROBE_BASE_BEHAVIOR_IMA].value & RISCV= _HWPROBE_IMA_V) ... > > > > > > > > > > > > > > > > > > though personally for the "big ticket items" that get a l= etter to > > > > > > > > > themselves like V, i'd be tempted to pass `(getauxval(AT_= HWCAP), > > > > > > > > > probe_count, probes_ptr)` to the resolver, but i hear tha= t's > > > > > > > > > controversial :-) > > > > > > > > > > > > > > > > Hello, welcome to the fun! :) > > > > > > > > > > > > > > (sorry for the delay. i've been thinking :-) ) > > > > > > > > > > > > > > > What you're describing here is almost exactly what we did i= nside the > > > > > > > > vDSO function. The vDSO function acts as a front for a hand= ful of > > > > > > > > probe values that we've already completed and cached in use= rspace. We > > > > > > > > opted to make it a function, rather than exposing the data = itself via > > > > > > > > vDSO, so that we had future flexibility in what elements we= cached in > > > > > > > > userspace and their storage format. We can update the kerne= l as needed > > > > > > > > to cache the hottest things in userspace, even if that mean= s > > > > > > > > rearranging the data format, passing through some extra inf= ormation, > > > > > > > > or adding an extra snip of code. My hope is callers can dir= ectly > > > > > > > > interact with the vDSO function (though maybe as Richard su= ggested > > > > > > > > maybe with the help of a tidy inline helper), rather than t= rying to > > > > > > > > add a second layer of userspace caching. > > > > > > > > > > > > > > on reflection i think i might be too focused on the FMV use c= ase, in > > > > > > > part because we're looking at those compiler-generated ifuncs= for > > > > > > > arm64 on Android atm. i think i'm imagining a world where the= re's a > > > > > > > lot of that, and worrying about having to pay for the setup, = call, and > > > > > > > loop for each ifunc, and wondering why we don't just pay once= instead. > > > > > > > (as a bit of background context, Android "app" start is actua= lly a > > > > > > > dlopen() in a clone of an existing zygote process, and in gen= eral app > > > > > > > launch time is one of the key metrics anyone who's serious is > > > > > > > optimizing for. you'd be surprised how much of my life i spen= d > > > > > > > explaining to people that if they want dlopen() to be faster,= maybe > > > > > > > they shouldn't ask us to run thousands of ELF constructors.) > > > > > > > > > > > > > > but... the more time i spend looking at what we actually need= in > > > > > > > third-party open source libraries right now i realize that li= bc and > > > > > > > FMV (which is still a future thing for us anyway) are really = the only > > > > > > > _actual_ ifunc users. perhaps in part because macOS/iOS don't= have > > > > > > > ifuncs, all the libraries that are part of the OS itself, for= example, > > > > > > > are just doing their own thing with function pointers and > > > > > > > pthread_once() or whatever. > > > > > > > > > > > > > > (i have yet to try to get any data on actual apps. i have no = reason to > > > > > > > think they'll be very different, but that could easily be ske= wed by > > > > > > > popular middleware or a popular game engine using ifuncs, so = i do plan > > > > > > > on following up on that.) > > > > > > > > > > > > > > "how do they decide what to set that function pointer to?". w= ell, it > > > > > > > looks like in most cases cpuid on x86 and calls to getauxval(= ) > > > > > > > everywhere else. in some cases that's actually via some other= library: > > > > > > > https://github.com/pytorch/cpuinfo or > > > > > > > https://github.com/google/cpu_features for example. so they h= ave a > > > > > > > layer of caching there, even in cases where they don't have a= single > > > > > > > function that sets all the function pointers. > > > > > > > > > > > > Right, function multi-versioning is just the sort of spot where= we'd > > > > > > imagine hwprobe gets used, since it's providing similar/equival= ent > > > > > > information to what cpuid does on x86. It may not be quite as f= ast as > > > > > > cpuid (I don't know how fast cpuid actually is). But with the v= DSO > > > > > > function+data in userspace it should be able to match getauxval= () in > > > > > > performance, as they're both a function pointer plus a loop. We= 're > > > > > > sort of planning for a world in which RISC-V has a wider set of= these > > > > > > values to fetch, such that a ifunc selector may need a more com= plex > > > > > > set of information. Hwprobe and the vDSO gives us the ability b= oth to > > > > > > answer multiple queries fast, and freely allocate more keys tha= t may > > > > > > represent versioned features or even compound features. > > > > > > > > > > yeah, my incorrect mental model was that -- primarily because of > > > > > x86-64 and cpuid -- every function would get its own ifunc resolv= er > > > > > that would have to make a query. but the [in progress] arm64 > > > > > implementation shows that that's not really the case anyway, and = we > > > > > can just cache __riscv_hwprobe() in the same [one] place that > > > > > getauxval() is already being cached for arm64. > > > > > > > > Sounds good. > > > > > > > > > > > > > > > > so assuming i don't find that apps look very different from t= he OS > > > > > > > (that is: that apps use lots of ifuncs), i probably don't car= e at all > > > > > > > until we get to FMV. and i probably don't care for FMV, becau= se > > > > > > > compiler-rt (or gcc's equivalent) will be the "caching layer"= there. > > > > > > > (and on Android it'll be a while before i have to worry about= libc's > > > > > > > ifuncs because we'll require V and not use ifuncs there for t= he > > > > > > > foreseeable future.) > > > > > > > > > > > > > > so, yeah, given that i've adopted the "pass a null pointer ra= ther than > > > > > > > no arguments" convention you have, we have room for expansion= if/when > > > > > > > FMV is a big thing, and until then -- unless i'm shocked by w= hat i > > > > > > > find looking at actual apps -- i don't think i have any reaso= n to > > > > > > > believe that ifuncs matter that much, and if compiler-rt make= s one > > > > > > > __riscv_hwprobe() call per .so, that's probably fine. (i alre= ady spend > > > > > > > a big chunk of my life advising people to just have one .so f= ile, > > > > > > > exporting nothing but a JNI_OnLoad symbol, so this will just = make that > > > > > > > advice even better advice :-) ) > > > > > > > > > > > > Just to confirm, by "pass a null pointer", you're saying that t= he > > > > > > Android libc also passes NULL as the second ifunc selector argu= ment > > > > > > (or first)? > > > > > > > > > > #elif defined(__riscv) > > > > > // This argument and its value is just a placeholder for now, > > > > > // but it means that if we do pass something in future (such as > > > > > // getauxval() and/or hwprobe key/value pairs), callees will be= able to > > > > > // recognize what they're being given. > > > > > typedef ElfW(Addr) (*ifunc_resolver_t)(void*); > > > > > return reinterpret_cast(resolver_addr)(nullpt= r); > > > > > > > > > > it's arm64 that has the initial getauxval() argument: > > > > > > > > > > #if defined(__aarch64__) > > > > > typedef ElfW(Addr) (*ifunc_resolver_t)(uint64_t, __ifunc_arg_t*= ); > > > > > static __ifunc_arg_t arg; > > > > > static bool initialized =3D false; > > > > > if (!initialized) { > > > > > initialized =3D true; > > > > > arg._size =3D sizeof(__ifunc_arg_t); > > > > > arg._hwcap =3D getauxval(AT_HWCAP); > > > > > arg._hwcap2 =3D getauxval(AT_HWCAP2); > > > > > } > > > > > return reinterpret_cast(resolver_addr)(arg._h= wcap > > > > > | _IFUNC_ARG_HWCAP, &arg); > > > > > > > > > > https://android.googlesource.com/platform/bionic/+/main/libc/bion= ic/bionic_call_ifunc_resolver.cpp > > > > > > > > > > > That's good. It sounds like you're planning to just > > > > > > continue passing NULL for now, and wait for people to start cla= moring > > > > > > for this in android libc? > > > > > > > > > > yeah, and i'm assuming there will never be any clamor ... yesterd= ay > > > > > and today i actually checked a bunch of popular apks, and didn't = find > > > > > any that were currently using ifuncs. > > > > > > > > > > the only change i'm thinking of making right now is that "there's= a > > > > > single argument, and it's null" should probably be the default. > > > > > obviously since Android doesn't add new architectures very often,= this > > > > > is only likely to affect x86/x86-64 for the foreseeable future, b= ut > > > > > being able to recognize at a glance "am i running under a libc ne= w > > > > > enough to pass me arguments?" would certainly have helped for arm= 64. > > > > > even if x86/x86-64 never benefit, it seems like the right default= for > > > > > the #else clause... > > > > > > > > Sounds good, thanks for the pointers. The paranoid person in me wou= ld > > > > also add a comment in the risc-v section that if a pointer to hwpro= be > > > > is added, it should be added as the second argument, behind hwcap a= s > > > > the first (assuming this change lands). > > > > > > > > Come to think of it, the static inline helper I'm proposing in my > > > > discussion with Richard needs to take both arguments, since callers > > > > need to check both ((arg1 !=3D 0) && (arg2 !=3D NULL)) to safely kn= ow that > > > > arg2 is a pointer to __riscv_hwprobe(). > > > > > > presumably not `(arg1 !=3D 0)` but `(arg1 & _IFUNC_ARG_HWCAP)` to mat= ch arm64? > > > > It looks like we didn't do that _IFUNC_ARG_HWCAP bit on riscv. > > Actually, looking at the history of sysdeps/riscv/dl-irel.h, hwcap has > > always been passed as the first argument. So I think I don't need to > > check it in the (glibc-specific) inline helper function, I can safely > > assume it's there and go straight to checking the second argument. > > oh i misunderstood what you were saying earlier. My bad for causing confusion, I learned something from your reply and changed my conclusion. > > > If you were coding this directly in a library or application, you > > would need to check the first arg to be compatible with other libcs > > like Android's. > > we haven't shipped yet, so if you're telling me glibc is passing > `(getauxval(AT_HWCAP), nullptr)`, i'll change bionic to do the same > today ... the whole reason i'm here on this thread is to ensure source > compatibility for anyone writing ifuncs :-) Ah, yes, they are (and have always on risc-v) passed (getauxval(AT_HWCAP), nullptr), so do exactly that. -Evan